llvm/test/CodeGen/AArch64/sve-llrint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s

define <vscale x 1 x i64> @llrint_v1i64_v1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v1f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.h, p0/m, z0.h
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    ret
  %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f16(<vscale x 1 x half> %x)
  ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f16(<vscale x 1 x half>)

define <vscale x 2 x i64> @llrint_v1i64_v2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: llrint_v1i64_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.h, p0/m, z0.h
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f16(<vscale x 2 x half> %x)
  ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f16(<vscale x 2 x half>)

define <vscale x 4 x i64> @llrint_v4i64_v4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: llrint_v4i64_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z1.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z1.h, p0/m, z1.h
; CHECK-NEXT:    movprfx z2, z0
; CHECK-NEXT:    frintx z2.h, p0/m, z0.h
; CHECK-NEXT:    movprfx z0, z1
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.h
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT:    ret
  %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half> %x)
  ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f16(<vscale x 4 x half>)

define <vscale x 8 x i64> @llrint_v8i64_v8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z1.s, z0.h
; CHECK-NEXT:    uunpkhi z0.s, z0.h
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpklo z2.d, z1.s
; CHECK-NEXT:    uunpkhi z1.d, z1.s
; CHECK-NEXT:    uunpklo z3.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    frintx z1.h, p0/m, z1.h
; CHECK-NEXT:    frintx z2.h, p0/m, z2.h
; CHECK-NEXT:    frintx z3.h, p0/m, z3.h
; CHECK-NEXT:    movprfx z4, z0
; CHECK-NEXT:    frintx z4.h, p0/m, z0.h
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
; CHECK-NEXT:    movprfx z0, z2
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z2.h
; CHECK-NEXT:    movprfx z2, z3
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z3.h
; CHECK-NEXT:    movprfx z3, z4
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z4.h
; CHECK-NEXT:    ret
  %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half> %x)
  ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f16(<vscale x 8 x half>)

define <vscale x 16 x i64> @llrint_v16i64_v16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z2.s, z0.h
; CHECK-NEXT:    uunpkhi z0.s, z0.h
; CHECK-NEXT:    uunpklo z3.s, z1.h
; CHECK-NEXT:    uunpkhi z1.s, z1.h
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpklo z4.d, z2.s
; CHECK-NEXT:    uunpkhi z2.d, z2.s
; CHECK-NEXT:    uunpklo z5.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    uunpklo z6.d, z3.s
; CHECK-NEXT:    uunpkhi z3.d, z3.s
; CHECK-NEXT:    uunpklo z7.d, z1.s
; CHECK-NEXT:    uunpkhi z1.d, z1.s
; CHECK-NEXT:    frintx z4.h, p0/m, z4.h
; CHECK-NEXT:    frintx z2.h, p0/m, z2.h
; CHECK-NEXT:    frintx z5.h, p0/m, z5.h
; CHECK-NEXT:    movprfx z24, z0
; CHECK-NEXT:    frintx z24.h, p0/m, z0.h
; CHECK-NEXT:    frintx z6.h, p0/m, z6.h
; CHECK-NEXT:    movprfx z25, z3
; CHECK-NEXT:    frintx z25.h, p0/m, z3.h
; CHECK-NEXT:    frintx z7.h, p0/m, z7.h
; CHECK-NEXT:    movprfx z26, z1
; CHECK-NEXT:    frintx z26.h, p0/m, z1.h
; CHECK-NEXT:    movprfx z0, z4
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z4.h
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z2.h
; CHECK-NEXT:    movprfx z2, z5
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z5.h
; CHECK-NEXT:    movprfx z3, z24
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z24.h
; CHECK-NEXT:    movprfx z4, z6
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z6.h
; CHECK-NEXT:    movprfx z5, z25
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z25.h
; CHECK-NEXT:    movprfx z6, z7
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z7.h
; CHECK-NEXT:    movprfx z7, z26
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z26.h
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half> %x)
  ret <vscale x 16 x i64> %a
}
declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f16(<vscale x 16 x half>)

define <vscale x 32 x i64> @llrint_v32i64_v32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpkhi z4.s, z3.h
; CHECK-NEXT:    uunpklo z3.s, z3.h
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpkhi z7.s, z2.h
; CHECK-NEXT:    uunpklo z2.s, z2.h
; CHECK-NEXT:    uunpkhi z24.s, z0.h
; CHECK-NEXT:    uunpkhi z25.s, z1.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpkhi z5.d, z4.s
; CHECK-NEXT:    uunpklo z4.d, z4.s
; CHECK-NEXT:    uunpkhi z6.d, z3.s
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    uunpkhi z26.d, z7.s
; CHECK-NEXT:    uunpklo z7.d, z7.s
; CHECK-NEXT:    uunpkhi z27.d, z2.s
; CHECK-NEXT:    uunpkhi z28.d, z24.s
; CHECK-NEXT:    uunpklo z2.d, z2.s
; CHECK-NEXT:    uunpkhi z29.d, z25.s
; CHECK-NEXT:    uunpklo z25.d, z25.s
; CHECK-NEXT:    frintx z5.h, p0/m, z5.h
; CHECK-NEXT:    frintx z4.h, p0/m, z4.h
; CHECK-NEXT:    frintx z6.h, p0/m, z6.h
; CHECK-NEXT:    frintx z3.h, p0/m, z3.h
; CHECK-NEXT:    frintx z26.h, p0/m, z26.h
; CHECK-NEXT:    frintx z7.h, p0/m, z7.h
; CHECK-NEXT:    frintx z27.h, p0/m, z27.h
; CHECK-NEXT:    frintx z2.h, p0/m, z2.h
; CHECK-NEXT:    frintx z28.h, p0/m, z28.h
; CHECK-NEXT:    frintx z29.h, p0/m, z29.h
; CHECK-NEXT:    frintx z25.h, p0/m, z25.h
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.h
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.h
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.h
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
; CHECK-NEXT:    fcvtzs z26.d, p0/m, z26.h
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.h
; CHECK-NEXT:    fcvtzs z27.d, p0/m, z27.h
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.h
; CHECK-NEXT:    fcvtzs z28.d, p0/m, z28.h
; CHECK-NEXT:    fcvtzs z29.d, p0/m, z29.h
; CHECK-NEXT:    fcvtzs z25.d, p0/m, z25.h
; CHECK-NEXT:    str z5, [x8, #15, mul vl]
; CHECK-NEXT:    uunpkhi z5.d, z1.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    str z4, [x8, #14, mul vl]
; CHECK-NEXT:    uunpkhi z4.d, z0.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    str z3, [x8, #12, mul vl]
; CHECK-NEXT:    uunpklo z3.d, z24.s
; CHECK-NEXT:    str z6, [x8, #13, mul vl]
; CHECK-NEXT:    str z26, [x8, #11, mul vl]
; CHECK-NEXT:    frintx z5.h, p0/m, z5.h
; CHECK-NEXT:    frintx z1.h, p0/m, z1.h
; CHECK-NEXT:    str z7, [x8, #10, mul vl]
; CHECK-NEXT:    frintx z4.h, p0/m, z4.h
; CHECK-NEXT:    frintx z0.h, p0/m, z0.h
; CHECK-NEXT:    str z27, [x8, #9, mul vl]
; CHECK-NEXT:    frintx z3.h, p0/m, z3.h
; CHECK-NEXT:    str z2, [x8, #8, mul vl]
; CHECK-NEXT:    str z29, [x8, #7, mul vl]
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.h
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
; CHECK-NEXT:    str z25, [x8, #6, mul vl]
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.h
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    str z28, [x8, #3, mul vl]
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
; CHECK-NEXT:    str z5, [x8, #5, mul vl]
; CHECK-NEXT:    str z1, [x8, #4, mul vl]
; CHECK-NEXT:    str z3, [x8, #2, mul vl]
; CHECK-NEXT:    str z4, [x8, #1, mul vl]
; CHECK-NEXT:    str z0, [x8]
; CHECK-NEXT:    ret
  %a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f16(<vscale x 32 x half> %x)
  ret <vscale x 32 x i64> %a
}
declare <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f16(<vscale x 32 x half>)

define <vscale x 1 x i64> @llrint_v1i64_v1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: llrint_v1i64_v1f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.s, p0/m, z0.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    ret
  %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float> %x)
  ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f32(<vscale x 1 x float>)

define <vscale x 2 x i64> @llrint_v2i64_v2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: llrint_v2i64_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.s, p0/m, z0.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float> %x)
  ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f32(<vscale x 2 x float>)

define <vscale x 4 x i64> @llrint_v4i64_v4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: llrint_v4i64_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z1.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z1.s, p0/m, z1.s
; CHECK-NEXT:    movprfx z2, z0
; CHECK-NEXT:    frintx z2.s, p0/m, z0.s
; CHECK-NEXT:    movprfx z0, z1
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z1.s
; CHECK-NEXT:    movprfx z1, z2
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z2.s
; CHECK-NEXT:    ret
  %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float> %x)
  ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f32(<vscale x 4 x float>)

define <vscale x 8 x i64> @llrint_v8i64_v8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: llrint_v8i64_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z2.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    uunpklo z3.d, z1.s
; CHECK-NEXT:    uunpkhi z1.d, z1.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z2.s, p0/m, z2.s
; CHECK-NEXT:    movprfx z4, z0
; CHECK-NEXT:    frintx z4.s, p0/m, z0.s
; CHECK-NEXT:    frintx z3.s, p0/m, z3.s
; CHECK-NEXT:    movprfx z5, z1
; CHECK-NEXT:    frintx z5.s, p0/m, z1.s
; CHECK-NEXT:    movprfx z0, z2
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z2.s
; CHECK-NEXT:    movprfx z1, z4
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z4.s
; CHECK-NEXT:    movprfx z2, z3
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z3.s
; CHECK-NEXT:    movprfx z3, z5
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z5.s
; CHECK-NEXT:    ret
  %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float> %x)
  ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f32(<vscale x 8 x float>)

define <vscale x 16 x i64> @llrint_v16i64_v16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpklo z4.d, z0.s
; CHECK-NEXT:    uunpkhi z0.d, z0.s
; CHECK-NEXT:    uunpklo z5.d, z1.s
; CHECK-NEXT:    uunpkhi z1.d, z1.s
; CHECK-NEXT:    uunpklo z6.d, z2.s
; CHECK-NEXT:    uunpkhi z2.d, z2.s
; CHECK-NEXT:    uunpklo z7.d, z3.s
; CHECK-NEXT:    uunpkhi z3.d, z3.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z4.s, p0/m, z4.s
; CHECK-NEXT:    movprfx z24, z0
; CHECK-NEXT:    frintx z24.s, p0/m, z0.s
; CHECK-NEXT:    frintx z5.s, p0/m, z5.s
; CHECK-NEXT:    movprfx z25, z1
; CHECK-NEXT:    frintx z25.s, p0/m, z1.s
; CHECK-NEXT:    frintx z6.s, p0/m, z6.s
; CHECK-NEXT:    movprfx z26, z2
; CHECK-NEXT:    frintx z26.s, p0/m, z2.s
; CHECK-NEXT:    frintx z7.s, p0/m, z7.s
; CHECK-NEXT:    movprfx z27, z3
; CHECK-NEXT:    frintx z27.s, p0/m, z3.s
; CHECK-NEXT:    movprfx z0, z4
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z4.s
; CHECK-NEXT:    movprfx z1, z24
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z24.s
; CHECK-NEXT:    movprfx z2, z5
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z5.s
; CHECK-NEXT:    movprfx z3, z25
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z25.s
; CHECK-NEXT:    movprfx z4, z6
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z6.s
; CHECK-NEXT:    movprfx z5, z26
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z26.s
; CHECK-NEXT:    movprfx z6, z7
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z7.s
; CHECK-NEXT:    movprfx z7, z27
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z27.s
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float> %x)
  ret <vscale x 16 x i64> %a
}
declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f32(<vscale x 16 x float>)

define <vscale x 32 x i64> @llrint_v32i64_v32f32(<vscale x 32 x float> %x) {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    uunpkhi z24.d, z7.s
; CHECK-NEXT:    uunpkhi z25.d, z6.s
; CHECK-NEXT:    uunpklo z6.d, z6.s
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    uunpklo z7.d, z7.s
; CHECK-NEXT:    uunpkhi z26.d, z5.s
; CHECK-NEXT:    uunpklo z5.d, z5.s
; CHECK-NEXT:    uunpkhi z27.d, z4.s
; CHECK-NEXT:    uunpkhi z28.d, z1.s
; CHECK-NEXT:    uunpklo z4.d, z4.s
; CHECK-NEXT:    uunpkhi z29.d, z3.s
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    frintx z24.s, p0/m, z24.s
; CHECK-NEXT:    frintx z6.s, p0/m, z6.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    frintx z7.s, p0/m, z7.s
; CHECK-NEXT:    frintx z25.s, p0/m, z25.s
; CHECK-NEXT:    frintx z26.s, p0/m, z26.s
; CHECK-NEXT:    frintx z5.s, p0/m, z5.s
; CHECK-NEXT:    frintx z27.s, p0/m, z27.s
; CHECK-NEXT:    frintx z28.s, p0/m, z28.s
; CHECK-NEXT:    frintx z4.s, p0/m, z4.s
; CHECK-NEXT:    frintx z29.s, p0/m, z29.s
; CHECK-NEXT:    frintx z3.s, p0/m, z3.s
; CHECK-NEXT:    fcvtzs z24.d, p0/m, z24.s
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.s
; CHECK-NEXT:    frintx z1.s, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.s
; CHECK-NEXT:    fcvtzs z25.d, p0/m, z25.s
; CHECK-NEXT:    fcvtzs z26.d, p0/m, z26.s
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.s
; CHECK-NEXT:    fcvtzs z27.d, p0/m, z27.s
; CHECK-NEXT:    fcvtzs z28.d, p0/m, z28.s
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
; CHECK-NEXT:    fcvtzs z29.d, p0/m, z29.s
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.s
; CHECK-NEXT:    str z24, [x8, #15, mul vl]
; CHECK-NEXT:    uunpkhi z24.d, z2.s
; CHECK-NEXT:    uunpklo z2.d, z2.s
; CHECK-NEXT:    str z6, [x8, #12, mul vl]
; CHECK-NEXT:    uunpkhi z6.d, z0.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    str z7, [x8, #14, mul vl]
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.s
; CHECK-NEXT:    str z25, [x8, #13, mul vl]
; CHECK-NEXT:    str z26, [x8, #11, mul vl]
; CHECK-NEXT:    frintx z24.s, p0/m, z24.s
; CHECK-NEXT:    frintx z2.s, p0/m, z2.s
; CHECK-NEXT:    str z5, [x8, #10, mul vl]
; CHECK-NEXT:    frintx z6.s, p0/m, z6.s
; CHECK-NEXT:    frintx z0.s, p0/m, z0.s
; CHECK-NEXT:    str z27, [x8, #9, mul vl]
; CHECK-NEXT:    str z4, [x8, #8, mul vl]
; CHECK-NEXT:    str z29, [x8, #7, mul vl]
; CHECK-NEXT:    fcvtzs z24.d, p0/m, z24.s
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.s
; CHECK-NEXT:    str z3, [x8, #6, mul vl]
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    str z28, [x8, #3, mul vl]
; CHECK-NEXT:    str z1, [x8, #2, mul vl]
; CHECK-NEXT:    str z24, [x8, #5, mul vl]
; CHECK-NEXT:    str z2, [x8, #4, mul vl]
; CHECK-NEXT:    str z6, [x8, #1, mul vl]
; CHECK-NEXT:    str z0, [x8]
; CHECK-NEXT:    ret
  %a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f32(<vscale x 32 x float> %x)
  ret <vscale x 32 x i64> %a
}
declare <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f32(<vscale x 32 x float>)

define <vscale x 1 x i64> @llrint_v1i64_v1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: llrint_v1i64_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %a = call <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double> %x)
  ret <vscale x 1 x i64> %a
}
declare <vscale x 1 x i64> @llvm.llrint.nxv1i64.nxv1f64(<vscale x 1 x double>)

define <vscale x 2 x i64> @llrint_v2i64_v2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: llrint_v2i64_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    ret
  %a = call <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double> %x)
  ret <vscale x 2 x i64> %a
}
declare <vscale x 2 x i64> @llvm.llrint.nxv2i64.nxv2f64(<vscale x 2 x double>)

define <vscale x 4 x i64> @llrint_v4i64_v4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: llrint_v4i64_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    frintx z1.d, p0/m, z1.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT:    ret
  %a = call <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double> %x)
  ret <vscale x 4 x i64> %a
}
declare <vscale x 4 x i64> @llvm.llrint.nxv4i64.nxv4f64(<vscale x 4 x double>)

define <vscale x 8 x i64> @llrint_v8i64_v8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: llrint_v8i64_v8f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    frintx z1.d, p0/m, z1.d
; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
; CHECK-NEXT:    frintx z3.d, p0/m, z3.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT:    ret
  %a = call <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double> %x)
  ret <vscale x 8 x i64> %a
}
declare <vscale x 8 x i64> @llvm.llrint.nxv8i64.nxv8f64(<vscale x 8 x double>)

define <vscale x 16 x i64> @llrint_v16f64(<vscale x 16 x double> %x) {
; CHECK-LABEL: llrint_v16f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    frintx z1.d, p0/m, z1.d
; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
; CHECK-NEXT:    frintx z3.d, p0/m, z3.d
; CHECK-NEXT:    frintx z4.d, p0/m, z4.d
; CHECK-NEXT:    frintx z5.d, p0/m, z5.d
; CHECK-NEXT:    frintx z6.d, p0/m, z6.d
; CHECK-NEXT:    frintx z7.d, p0/m, z7.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.d
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT:    ret
  %a = call <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double> %x)
  ret <vscale x 16 x i64> %a
}
declare <vscale x 16 x i64> @llvm.llrint.nxv16i64.nxv16f64(<vscale x 16 x double>)

define <vscale x 32 x i64> @llrint_v32f64(<vscale x 32 x double> %x) {
; CHECK-LABEL: llrint_v32f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr z0, [x0, #15, mul vl]
; CHECK-NEXT:    ldr z1, [x0, #14, mul vl]
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    ldr z2, [x0, #13, mul vl]
; CHECK-NEXT:    ldr z3, [x0, #12, mul vl]
; CHECK-NEXT:    ldr z4, [x0, #11, mul vl]
; CHECK-NEXT:    ldr z5, [x0, #10, mul vl]
; CHECK-NEXT:    ldr z6, [x0, #9, mul vl]
; CHECK-NEXT:    ldr z7, [x0, #8, mul vl]
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    frintx z1.d, p0/m, z1.d
; CHECK-NEXT:    ldr z24, [x0, #7, mul vl]
; CHECK-NEXT:    ldr z25, [x0, #6, mul vl]
; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
; CHECK-NEXT:    frintx z3.d, p0/m, z3.d
; CHECK-NEXT:    ldr z26, [x0, #5, mul vl]
; CHECK-NEXT:    ldr z27, [x0, #4, mul vl]
; CHECK-NEXT:    frintx z4.d, p0/m, z4.d
; CHECK-NEXT:    ldr z28, [x0, #3, mul vl]
; CHECK-NEXT:    ldr z29, [x0, #2, mul vl]
; CHECK-NEXT:    frintx z5.d, p0/m, z5.d
; CHECK-NEXT:    ldr z30, [x0, #1, mul vl]
; CHECK-NEXT:    ldr z31, [x0]
; CHECK-NEXT:    frintx z6.d, p0/m, z6.d
; CHECK-NEXT:    frintx z7.d, p0/m, z7.d
; CHECK-NEXT:    frintx z24.d, p0/m, z24.d
; CHECK-NEXT:    frintx z25.d, p0/m, z25.d
; CHECK-NEXT:    frintx z26.d, p0/m, z26.d
; CHECK-NEXT:    frintx z27.d, p0/m, z27.d
; CHECK-NEXT:    frintx z28.d, p0/m, z28.d
; CHECK-NEXT:    frintx z29.d, p0/m, z29.d
; CHECK-NEXT:    frintx z30.d, p0/m, z30.d
; CHECK-NEXT:    frintx z31.d, p0/m, z31.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.d
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.d
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.d
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.d
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.d
; CHECK-NEXT:    fcvtzs z24.d, p0/m, z24.d
; CHECK-NEXT:    fcvtzs z25.d, p0/m, z25.d
; CHECK-NEXT:    fcvtzs z26.d, p0/m, z26.d
; CHECK-NEXT:    fcvtzs z27.d, p0/m, z27.d
; CHECK-NEXT:    fcvtzs z28.d, p0/m, z28.d
; CHECK-NEXT:    fcvtzs z29.d, p0/m, z29.d
; CHECK-NEXT:    fcvtzs z30.d, p0/m, z30.d
; CHECK-NEXT:    fcvtzs z31.d, p0/m, z31.d
; CHECK-NEXT:    str z0, [x8, #15, mul vl]
; CHECK-NEXT:    str z1, [x8, #14, mul vl]
; CHECK-NEXT:    str z2, [x8, #13, mul vl]
; CHECK-NEXT:    str z3, [x8, #12, mul vl]
; CHECK-NEXT:    str z4, [x8, #11, mul vl]
; CHECK-NEXT:    str z5, [x8, #10, mul vl]
; CHECK-NEXT:    str z6, [x8, #9, mul vl]
; CHECK-NEXT:    str z7, [x8, #8, mul vl]
; CHECK-NEXT:    str z24, [x8, #7, mul vl]
; CHECK-NEXT:    str z25, [x8, #6, mul vl]
; CHECK-NEXT:    str z26, [x8, #5, mul vl]
; CHECK-NEXT:    str z27, [x8, #4, mul vl]
; CHECK-NEXT:    str z28, [x8, #3, mul vl]
; CHECK-NEXT:    str z29, [x8, #2, mul vl]
; CHECK-NEXT:    str z30, [x8, #1, mul vl]
; CHECK-NEXT:    str z31, [x8]
; CHECK-NEXT:    ret
  %a = call <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv16f64(<vscale x 32 x double> %x)
  ret <vscale x 32 x i64> %a
}
declare <vscale x 32 x i64> @llvm.llrint.nxv32i64.nxv32f64(<vscale x 32 x double>)