llvm/test/CodeGen/AArch64/sve-fixed-vector-llrint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -mattr=+sve -aarch64-sve-vector-bits-min=256 | FileCheck %s

define <1 x i64> @llrint_v1i64_v1f16(<1 x half> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v1f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx h0, h0
; CHECK-NEXT:    fcvtzs x8, h0
; CHECK-NEXT:    fmov d0, x8
; CHECK-NEXT:    ret
  %a = call <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half> %x)
  ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f16(<1 x half>)

define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    mov h1, v0.h[1]
; CHECK-NEXT:    frintx h0, h0
; CHECK-NEXT:    frintx h1, h1
; CHECK-NEXT:    fcvtzs x8, h0
; CHECK-NEXT:    fcvtzs x9, h1
; CHECK-NEXT:    fmov d0, x8
; CHECK-NEXT:    mov v0.d[1], x9
; CHECK-NEXT:    ret
  %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
  ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)

define <4 x i64> @llrint_v4i64_v4f16(<4 x half> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v0.4h, v0.4h
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %a = call <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half> %x)
  ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f16(<4 x half>)

define <8 x i64> @llrint_v8i64_v8f16(<8 x half> %x) nounwind {
; CHECK-LABEL: llrint_v8i64_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov d1, v0.d[1]
; CHECK-NEXT:    frintx v0.4h, v0.4h
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx v1.4h, v1.4h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    movprfx z2, z1
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z1.h
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    ret
  %a = call <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half> %x)
  ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f16(<8 x half>)

define <16 x i64> @llrint_v16i64_v16f16(<16 x half> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov d2, v0.d[1]
; CHECK-NEXT:    mov d3, v1.d[1]
; CHECK-NEXT:    frintx v0.4h, v0.4h
; CHECK-NEXT:    frintx v1.4h, v1.4h
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx v2.4h, v2.4h
; CHECK-NEXT:    frintx v3.4h, v3.4h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpklo z2.s, z2.h
; CHECK-NEXT:    uunpklo z3.s, z3.h
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpklo z2.d, z2.s
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    movprfx z4, z1
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z1.h
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.h
; CHECK-NEXT:    movprfx z6, z3
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z3.h
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    movprfx z5, z4
; CHECK-NEXT:    ext z5.b, z5.b, z4.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q4 killed $q4 killed $z4
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    movprfx z7, z6
; CHECK-NEXT:    ext z7.b, z7.b, z6.b, #16
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT:    // kill: def $q6 killed $q6 killed $z6
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT:    ret
  %a = call <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half> %x)
  ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f16(<16 x half>)

define <32 x i64> @llrint_v32i64_v32f16(<32 x half> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov d4, v3.d[1]
; CHECK-NEXT:    mov d5, v2.d[1]
; CHECK-NEXT:    mov x9, #28 // =0x1c
; CHECK-NEXT:    mov d6, v1.d[1]
; CHECK-NEXT:    frintx v3.4h, v3.4h
; CHECK-NEXT:    mov d7, v0.d[1]
; CHECK-NEXT:    frintx v2.4h, v2.4h
; CHECK-NEXT:    frintx v1.4h, v1.4h
; CHECK-NEXT:    frintx v0.4h, v0.4h
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx v4.4h, v4.4h
; CHECK-NEXT:    frintx v5.4h, v5.4h
; CHECK-NEXT:    frintx v6.4h, v6.4h
; CHECK-NEXT:    uunpklo z3.s, z3.h
; CHECK-NEXT:    frintx v7.4h, v7.4h
; CHECK-NEXT:    uunpklo z2.s, z2.h
; CHECK-NEXT:    uunpklo z1.s, z1.h
; CHECK-NEXT:    uunpklo z0.s, z0.h
; CHECK-NEXT:    uunpklo z4.s, z4.h
; CHECK-NEXT:    uunpklo z5.s, z5.h
; CHECK-NEXT:    uunpklo z6.s, z6.h
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    uunpklo z7.s, z7.h
; CHECK-NEXT:    uunpklo z2.d, z2.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    uunpklo z4.d, z4.s
; CHECK-NEXT:    uunpklo z5.d, z5.s
; CHECK-NEXT:    uunpklo z6.d, z6.s
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.h
; CHECK-NEXT:    uunpklo z7.d, z7.s
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.h
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.h
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.h
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.h
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.h
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.h
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.h
; CHECK-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #24 // =0x18
; CHECK-NEXT:    st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #20 // =0x14
; CHECK-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #16 // =0x10
; CHECK-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #12 // =0xc
; CHECK-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #8 // =0x8
; CHECK-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #4 // =0x4
; CHECK-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
; CHECK-NEXT:    ret
  %a = call <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half> %x)
  ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f16(<32 x half>)

define <1 x i64> @llrint_v1i64_v1f32(<1 x float> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v1f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    frintx s0, s0
; CHECK-NEXT:    fcvtzs x8, s0
; CHECK-NEXT:    fmov d0, x8
; CHECK-NEXT:    ret
  %a = call <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float> %x)
  ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f32(<1 x float>)

define <2 x i64> @llrint_v2i64_v2f32(<2 x float> %x) nounwind {
; CHECK-LABEL: llrint_v2i64_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v0.2s, v0.2s
; CHECK-NEXT:    fcvtl v0.2d, v0.2s
; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
; CHECK-NEXT:    ret
  %a = call <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float> %x)
  ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f32(<2 x float>)

define <4 x i64> @llrint_v4i64_v4f32(<4 x float> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v0.4s, v0.4s
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %a = call <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float> %x)
  ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f32(<4 x float>)

define <8 x i64> @llrint_v8i64_v8f32(<8 x float> %x) nounwind {
; CHECK-LABEL: llrint_v8i64_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v1.4s, v1.4s
; CHECK-NEXT:    frintx v0.4s, v0.4s
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    movprfx z2, z1
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    ret
  %a = call <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float> %x)
  ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f32(<8 x float>)

define <16 x i64> @llrint_v16i64_v16f32(<16 x float> %x) nounwind {
; CHECK-LABEL: llrint_v16i64_v16f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v1.4s, v1.4s
; CHECK-NEXT:    frintx v0.4s, v0.4s
; CHECK-NEXT:    frintx v3.4s, v3.4s
; CHECK-NEXT:    frintx v2.4s, v2.4s
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    uunpklo z4.d, z2.s
; CHECK-NEXT:    movprfx z2, z1
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    movprfx z6, z3
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z3.s
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    movprfx z7, z6
; CHECK-NEXT:    ext z7.b, z7.b, z6.b, #16
; CHECK-NEXT:    movprfx z5, z4
; CHECK-NEXT:    ext z5.b, z5.b, z4.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q4 killed $q4 killed $z4
; CHECK-NEXT:    // kill: def $q6 killed $q6 killed $z6
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT:    // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT:    ret
  %a = call <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float> %x)
  ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f32(<16 x float>)

define <32 x i64> @llrint_v32i64_v32f32(<32 x float> %x) nounwind {
; CHECK-LABEL: llrint_v32i64_v32f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v7.4s, v7.4s
; CHECK-NEXT:    frintx v6.4s, v6.4s
; CHECK-NEXT:    mov x9, #28 // =0x1c
; CHECK-NEXT:    frintx v5.4s, v5.4s
; CHECK-NEXT:    frintx v4.4s, v4.4s
; CHECK-NEXT:    frintx v3.4s, v3.4s
; CHECK-NEXT:    frintx v2.4s, v2.4s
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx v1.4s, v1.4s
; CHECK-NEXT:    frintx v0.4s, v0.4s
; CHECK-NEXT:    uunpklo z7.d, z7.s
; CHECK-NEXT:    uunpklo z6.d, z6.s
; CHECK-NEXT:    uunpklo z5.d, z5.s
; CHECK-NEXT:    uunpklo z4.d, z4.s
; CHECK-NEXT:    uunpklo z3.d, z3.s
; CHECK-NEXT:    uunpklo z2.d, z2.s
; CHECK-NEXT:    uunpklo z1.d, z1.s
; CHECK-NEXT:    uunpklo z0.d, z0.s
; CHECK-NEXT:    fcvtzs z7.d, p0/m, z7.s
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.s
; CHECK-NEXT:    fcvtzs z5.d, p0/m, z5.s
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.s
; CHECK-NEXT:    fcvtzs z3.d, p0/m, z3.s
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.s
; CHECK-NEXT:    fcvtzs z1.d, p0/m, z1.s
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.s
; CHECK-NEXT:    st1d { z7.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #24 // =0x18
; CHECK-NEXT:    st1d { z6.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #20 // =0x14
; CHECK-NEXT:    st1d { z5.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #16 // =0x10
; CHECK-NEXT:    st1d { z4.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #12 // =0xc
; CHECK-NEXT:    st1d { z3.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #8 // =0x8
; CHECK-NEXT:    st1d { z2.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #4 // =0x4
; CHECK-NEXT:    st1d { z1.d }, p0, [x8, x9, lsl #3]
; CHECK-NEXT:    st1d { z0.d }, p0, [x8]
; CHECK-NEXT:    ret
  %a = call <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float> %x)
  ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f32(<32 x float>)

define <1 x i64> @llrint_v1i64_v1f64(<1 x double> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx d0, d0
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %a = call <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double> %x)
  ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1f64(<1 x double>)

define <2 x i64> @llrint_v2i64_v2f64(<2 x double> %x) nounwind {
; CHECK-LABEL: llrint_v2i64_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    frintx v0.2d, v0.2d
; CHECK-NEXT:    fcvtzs v0.2d, v0.2d
; CHECK-NEXT:    ret
  %a = call <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double> %x)
  ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2f64(<2 x double>)

define <4 x i64> @llrint_v4i64_v4f64(<4 x double> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    ret
  %a = call <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double> %x)
  ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4f64(<4 x double>)

define <8 x i64> @llrint_v8i64_v8f64(<8 x double> %x) nounwind {
; CHECK-LABEL: llrint_v8i64_v8f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT:    splice z2.d, p0, z2.d, z3.d
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    ret
  %a = call <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double> %x)
  ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8f64(<8 x double>)

define <16 x i64> @llrint_v16f64(<16 x double> %x) nounwind {
; CHECK-LABEL: llrint_v16f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT:    // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT:    // kill: def $q5 killed $q5 def $z5
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT:    splice z2.d, p0, z2.d, z3.d
; CHECK-NEXT:    splice z4.d, p0, z4.d, z5.d
; CHECK-NEXT:    splice z6.d, p0, z6.d, z7.d
; CHECK-NEXT:    ptrue p0.d, vl4
; CHECK-NEXT:    frintx z2.d, p0/m, z2.d
; CHECK-NEXT:    frintx z0.d, p0/m, z0.d
; CHECK-NEXT:    frintx z4.d, p0/m, z4.d
; CHECK-NEXT:    frintx z6.d, p0/m, z6.d
; CHECK-NEXT:    fcvtzs z2.d, p0/m, z2.d
; CHECK-NEXT:    fcvtzs z0.d, p0/m, z0.d
; CHECK-NEXT:    fcvtzs z4.d, p0/m, z4.d
; CHECK-NEXT:    fcvtzs z6.d, p0/m, z6.d
; CHECK-NEXT:    movprfx z1, z0
; CHECK-NEXT:    ext z1.b, z1.b, z0.b, #16
; CHECK-NEXT:    movprfx z3, z2
; CHECK-NEXT:    ext z3.b, z3.b, z2.b, #16
; CHECK-NEXT:    movprfx z5, z4
; CHECK-NEXT:    ext z5.b, z5.b, z4.b, #16
; CHECK-NEXT:    movprfx z7, z6
; CHECK-NEXT:    ext z7.b, z7.b, z6.b, #16
; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT:    // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT:    // kill: def $q4 killed $q4 killed $z4
; CHECK-NEXT:    // kill: def $q6 killed $q6 killed $z6
; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT:    // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT:    // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT:    // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT:    ret
  %a = call <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double> %x)
  ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16f64(<16 x double>)

define <32 x i64> @llrint_v32f64(<32 x double> %x) nounwind {
; CHECK-LABEL: llrint_v32f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldp q17, q16, [sp, #96]
; CHECK-NEXT:    ptrue p0.d, vl2
; CHECK-NEXT:    ldp q19, q18, [sp, #64]
; CHECK-NEXT:    ptrue p1.d, vl4
; CHECK-NEXT:    // kill: def $q6 killed $q6 def $z6
; CHECK-NEXT:    // kill: def $q7 killed $q7 def $z7
; CHECK-NEXT:    // kill: def $q4 killed $q4 def $z4
; CHECK-NEXT:    // kill: def $q5 killed $q5 def $z5
; CHECK-NEXT:    // kill: def $q2 killed $q2 def $z2
; CHECK-NEXT:    // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT:    // kill: def $q3 killed $q3 def $z3
; CHECK-NEXT:    // kill: def $q1 killed $q1 def $z1
; CHECK-NEXT:    mov x9, #28 // =0x1c
; CHECK-NEXT:    splice z17.d, p0, z17.d, z16.d
; CHECK-NEXT:    ldp q20, q16, [sp, #32]
; CHECK-NEXT:    splice z19.d, p0, z19.d, z18.d
; CHECK-NEXT:    ldp q21, q18, [sp]
; CHECK-NEXT:    splice z6.d, p0, z6.d, z7.d
; CHECK-NEXT:    splice z4.d, p0, z4.d, z5.d
; CHECK-NEXT:    splice z2.d, p0, z2.d, z3.d
; CHECK-NEXT:    splice z20.d, p0, z20.d, z16.d
; CHECK-NEXT:    splice z0.d, p0, z0.d, z1.d
; CHECK-NEXT:    splice z21.d, p0, z21.d, z18.d
; CHECK-NEXT:    frintx z17.d, p1/m, z17.d
; CHECK-NEXT:    frintx z19.d, p1/m, z19.d
; CHECK-NEXT:    frintx z6.d, p1/m, z6.d
; CHECK-NEXT:    frintx z4.d, p1/m, z4.d
; CHECK-NEXT:    frintx z2.d, p1/m, z2.d
; CHECK-NEXT:    frintx z20.d, p1/m, z20.d
; CHECK-NEXT:    frintx z0.d, p1/m, z0.d
; CHECK-NEXT:    frintx z21.d, p1/m, z21.d
; CHECK-NEXT:    fcvtzs z17.d, p1/m, z17.d
; CHECK-NEXT:    fcvtzs z19.d, p1/m, z19.d
; CHECK-NEXT:    fcvtzs z6.d, p1/m, z6.d
; CHECK-NEXT:    fcvtzs z4.d, p1/m, z4.d
; CHECK-NEXT:    fcvtzs z2.d, p1/m, z2.d
; CHECK-NEXT:    fcvtzs z20.d, p1/m, z20.d
; CHECK-NEXT:    fcvtzs z0.d, p1/m, z0.d
; CHECK-NEXT:    fcvtzs z21.d, p1/m, z21.d
; CHECK-NEXT:    st1d { z17.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #24 // =0x18
; CHECK-NEXT:    st1d { z19.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #20 // =0x14
; CHECK-NEXT:    st1d { z20.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #16 // =0x10
; CHECK-NEXT:    st1d { z21.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #12 // =0xc
; CHECK-NEXT:    st1d { z6.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #8 // =0x8
; CHECK-NEXT:    st1d { z4.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    mov x9, #4 // =0x4
; CHECK-NEXT:    st1d { z2.d }, p1, [x8, x9, lsl #3]
; CHECK-NEXT:    st1d { z0.d }, p1, [x8]
; CHECK-NEXT:    ret
  %a = call <32 x i64> @llvm.llrint.v32i64.v16f64(<32 x double> %x)
  ret <32 x i64> %a
}
declare <32 x i64> @llvm.llrint.v32i64.v32f64(<32 x double>)

define <1 x i64> @llrint_v1i64_v1fp128(<1 x fp128> %x) nounwind {
; CHECK-LABEL: llrint_v1i64_v1fp128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %a = call <1 x i64> @llvm.llrint.v1i64.v1fp128(<1 x fp128> %x)
  ret <1 x i64> %a
}
declare <1 x i64> @llvm.llrint.v1i64.v1fp128(<1 x fp128>)

define <2 x i64> @llrint_v2i64_v2fp128(<2 x fp128> %x) nounwind {
; CHECK-LABEL: llrint_v2i64_v2fp128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #48
; CHECK-NEXT:    str q0, [sp] // 16-byte Spill
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    str x30, [sp, #32] // 8-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT:    ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    ldr q1, [sp, #16] // 16-byte Reload
; CHECK-NEXT:    ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT:    mov v0.d[1], v1.d[0]
; CHECK-NEXT:    add sp, sp, #48
; CHECK-NEXT:    ret
  %a = call <2 x i64> @llvm.llrint.v2i64.v2fp128(<2 x fp128> %x)
  ret <2 x i64> %a
}
declare <2 x i64> @llvm.llrint.v2i64.v2fp128(<2 x fp128>)

define <4 x i64> @llrint_v4i64_v4fp128(<4 x fp128> %x) nounwind {
; CHECK-LABEL: llrint_v4i64_v4fp128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #80
; CHECK-NEXT:    str x30, [sp, #48] // 8-byte Spill
; CHECK-NEXT:    stp x20, x19, [sp, #64] // 16-byte Folded Spill
; CHECK-NEXT:    stp q3, q2, [sp] // 32-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #32] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT:    mov x19, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT:    mov x20, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    fmov d1, x20
; CHECK-NEXT:    str q0, [sp] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x19
; CHECK-NEXT:    str q0, [sp, #16] // 16-byte Spill
; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Reload
; CHECK-NEXT:    str q1, [sp, #32] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldp q0, q4, [sp, #16] // 32-byte Folded Reload
; CHECK-NEXT:    fmov d2, x0
; CHECK-NEXT:    ldr q1, [sp] // 16-byte Reload
; CHECK-NEXT:    ldp x20, x19, [sp, #64] // 16-byte Folded Reload
; CHECK-NEXT:    ldr x30, [sp, #48] // 8-byte Reload
; CHECK-NEXT:    mov v1.d[1], v4.d[0]
; CHECK-NEXT:    mov v0.d[1], v2.d[0]
; CHECK-NEXT:    add sp, sp, #80
; CHECK-NEXT:    ret
  %a = call <4 x i64> @llvm.llrint.v4i64.v4fp128(<4 x fp128> %x)
  ret <4 x i64> %a
}
declare <4 x i64> @llvm.llrint.v4i64.v4fp128(<4 x fp128>)

define <8 x i64> @llrint_v8i64_v8fp128(<8 x fp128> %x) nounwind {
; CHECK-LABEL: llrint_v8i64_v8fp128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #176
; CHECK-NEXT:    str x30, [sp, #112] // 8-byte Spill
; CHECK-NEXT:    stp x24, x23, [sp, #128] // 16-byte Folded Spill
; CHECK-NEXT:    stp x22, x21, [sp, #144] // 16-byte Folded Spill
; CHECK-NEXT:    stp x20, x19, [sp, #160] // 16-byte Folded Spill
; CHECK-NEXT:    stp q3, q2, [sp] // 32-byte Folded Spill
; CHECK-NEXT:    stp q5, q4, [sp, #32] // 32-byte Folded Spill
; CHECK-NEXT:    stp q7, q6, [sp, #64] // 32-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #96] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp] // 16-byte Reload
; CHECK-NEXT:    mov x19, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT:    mov x20, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Reload
; CHECK-NEXT:    mov x21, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #48] // 16-byte Reload
; CHECK-NEXT:    mov x22, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #64] // 16-byte Reload
; CHECK-NEXT:    mov x23, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #80] // 16-byte Reload
; CHECK-NEXT:    mov x24, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    fmov d1, x24
; CHECK-NEXT:    str q0, [sp, #80] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x23
; CHECK-NEXT:    str q0, [sp, #64] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x21
; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x19
; CHECK-NEXT:    str q0, [sp] // 16-byte Spill
; CHECK-NEXT:    ldr q0, [sp, #96] // 16-byte Reload
; CHECK-NEXT:    str q1, [sp, #96] // 16-byte Spill
; CHECK-NEXT:    fmov d1, x22
; CHECK-NEXT:    str q1, [sp, #32] // 16-byte Spill
; CHECK-NEXT:    fmov d1, x20
; CHECK-NEXT:    str q1, [sp, #16] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d1, x0
; CHECK-NEXT:    ldp q0, q2, [sp] // 32-byte Folded Reload
; CHECK-NEXT:    ldp x20, x19, [sp, #160] // 16-byte Folded Reload
; CHECK-NEXT:    ldr x30, [sp, #112] // 8-byte Reload
; CHECK-NEXT:    ldp x22, x21, [sp, #144] // 16-byte Folded Reload
; CHECK-NEXT:    mov v0.d[1], v1.d[0]
; CHECK-NEXT:    ldp q3, q1, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT:    ldp x24, x23, [sp, #128] // 16-byte Folded Reload
; CHECK-NEXT:    mov v1.d[1], v2.d[0]
; CHECK-NEXT:    ldr q2, [sp, #64] // 16-byte Reload
; CHECK-NEXT:    mov v2.d[1], v3.d[0]
; CHECK-NEXT:    ldp q3, q4, [sp, #80] // 32-byte Folded Reload
; CHECK-NEXT:    mov v3.d[1], v4.d[0]
; CHECK-NEXT:    add sp, sp, #176
; CHECK-NEXT:    ret
  %a = call <8 x i64> @llvm.llrint.v8i64.v8fp128(<8 x fp128> %x)
  ret <8 x i64> %a
}
declare <8 x i64> @llvm.llrint.v8i64.v8fp128(<8 x fp128>)

define <16 x i64> @llrint_v16fp128(<16 x fp128> %x) nounwind {
; CHECK-LABEL: llrint_v16fp128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #368
; CHECK-NEXT:    stp q3, q1, [sp, #240] // 32-byte Folded Spill
; CHECK-NEXT:    ldr q1, [sp, #464]
; CHECK-NEXT:    stp x29, x30, [sp, #272] // 16-byte Folded Spill
; CHECK-NEXT:    stp q2, q4, [sp, #16] // 32-byte Folded Spill
; CHECK-NEXT:    stp q1, q5, [sp, #192] // 32-byte Folded Spill
; CHECK-NEXT:    ldr q1, [sp, #480]
; CHECK-NEXT:    stp x28, x27, [sp, #288] // 16-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #176] // 16-byte Spill
; CHECK-NEXT:    ldr q1, [sp, #432]
; CHECK-NEXT:    stp x26, x25, [sp, #304] // 16-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #160] // 16-byte Spill
; CHECK-NEXT:    ldr q1, [sp, #448]
; CHECK-NEXT:    stp x24, x23, [sp, #320] // 16-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #144] // 16-byte Spill
; CHECK-NEXT:    ldr q1, [sp, #400]
; CHECK-NEXT:    stp x22, x21, [sp, #336] // 16-byte Folded Spill
; CHECK-NEXT:    str q1, [sp, #128] // 16-byte Spill
; CHECK-NEXT:    ldr q1, [sp, #416]
; CHECK-NEXT:    stp x20, x19, [sp, #352] // 16-byte Folded Spill
; CHECK-NEXT:    stp q6, q1, [sp, #96] // 32-byte Folded Spill
; CHECK-NEXT:    ldr q1, [sp, #368]
; CHECK-NEXT:    stp q7, q1, [sp, #64] // 32-byte Folded Spill
; CHECK-NEXT:    ldr q1, [sp, #384]
; CHECK-NEXT:    str q1, [sp, #48] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #240] // 16-byte Reload
; CHECK-NEXT:    str x0, [sp, #224] // 8-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #16] // 16-byte Reload
; CHECK-NEXT:    str x0, [sp, #240] // 8-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #208] // 16-byte Reload
; CHECK-NEXT:    mov x22, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #32] // 16-byte Reload
; CHECK-NEXT:    str x0, [sp, #208] // 8-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #64] // 16-byte Reload
; CHECK-NEXT:    mov x24, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #96] // 16-byte Reload
; CHECK-NEXT:    mov x23, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #48] // 16-byte Reload
; CHECK-NEXT:    mov x25, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #80] // 16-byte Reload
; CHECK-NEXT:    mov x26, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #112] // 16-byte Reload
; CHECK-NEXT:    mov x27, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #128] // 16-byte Reload
; CHECK-NEXT:    mov x28, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #144] // 16-byte Reload
; CHECK-NEXT:    mov x29, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #160] // 16-byte Reload
; CHECK-NEXT:    mov x19, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #176] // 16-byte Reload
; CHECK-NEXT:    mov x20, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldr q0, [sp, #192] // 16-byte Reload
; CHECK-NEXT:    mov x21, x0
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    ldr x8, [sp, #224] // 8-byte Reload
; CHECK-NEXT:    fmov d1, x23
; CHECK-NEXT:    str q0, [sp, #192] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x21
; CHECK-NEXT:    str q0, [sp, #176] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x20
; CHECK-NEXT:    str q0, [sp, #160] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x19
; CHECK-NEXT:    str q0, [sp, #144] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x29
; CHECK-NEXT:    str q0, [sp, #128] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x27
; CHECK-NEXT:    str q0, [sp, #112] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x25
; CHECK-NEXT:    str q0, [sp, #96] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x24
; CHECK-NEXT:    str q0, [sp, #48] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x22
; CHECK-NEXT:    str q0, [sp, #32] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x8
; CHECK-NEXT:    str q0, [sp, #80] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x28
; CHECK-NEXT:    str q0, [sp, #224] // 16-byte Spill
; CHECK-NEXT:    fmov d0, x26
; CHECK-NEXT:    str q0, [sp, #64] // 16-byte Spill
; CHECK-NEXT:    ldr q0, [sp, #256] // 16-byte Reload
; CHECK-NEXT:    str q1, [sp, #256] // 16-byte Spill
; CHECK-NEXT:    ldr d1, [sp, #208] // 8-byte Reload
; CHECK-NEXT:    str q1, [sp, #208] // 16-byte Spill
; CHECK-NEXT:    ldr d1, [sp, #240] // 8-byte Reload
; CHECK-NEXT:    str q1, [sp, #240] // 16-byte Spill
; CHECK-NEXT:    bl llrintl
; CHECK-NEXT:    ldp q1, q2, [sp, #32] // 32-byte Folded Reload
; CHECK-NEXT:    ldr q5, [sp, #64] // 16-byte Reload
; CHECK-NEXT:    ldp q0, q4, [sp, #240] // 32-byte Folded Reload
; CHECK-NEXT:    ldp q16, q3, [sp, #80] // 32-byte Folded Reload
; CHECK-NEXT:    ldp x20, x19, [sp, #352] // 16-byte Folded Reload
; CHECK-NEXT:    mov v1.d[1], v0.d[0]
; CHECK-NEXT:    ldp q7, q0, [sp, #192] // 32-byte Folded Reload
; CHECK-NEXT:    mov v3.d[1], v4.d[0]
; CHECK-NEXT:    ldr q4, [sp, #112] // 16-byte Reload
; CHECK-NEXT:    ldp x22, x21, [sp, #336] // 16-byte Folded Reload
; CHECK-NEXT:    mov v2.d[1], v0.d[0]
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    mov v4.d[1], v5.d[0]
; CHECK-NEXT:    ldr q5, [sp, #128] // 16-byte Reload
; CHECK-NEXT:    ldp x24, x23, [sp, #320] // 16-byte Folded Reload
; CHECK-NEXT:    ldp x26, x25, [sp, #304] // 16-byte Folded Reload
; CHECK-NEXT:    mov v16.d[1], v0.d[0]
; CHECK-NEXT:    ldr q0, [sp, #224] // 16-byte Reload
; CHECK-NEXT:    ldp x28, x27, [sp, #288] // 16-byte Folded Reload
; CHECK-NEXT:    mov v5.d[1], v0.d[0]
; CHECK-NEXT:    ldp q0, q6, [sp, #144] // 32-byte Folded Reload
; CHECK-NEXT:    ldp x29, x30, [sp, #272] // 16-byte Folded Reload
; CHECK-NEXT:    mov v6.d[1], v0.d[0]
; CHECK-NEXT:    ldr q0, [sp, #176] // 16-byte Reload
; CHECK-NEXT:    mov v7.d[1], v0.d[0]
; CHECK-NEXT:    mov v0.16b, v16.16b
; CHECK-NEXT:    add sp, sp, #368
; CHECK-NEXT:    ret
  %a = call <16 x i64> @llvm.llrint.v16i64.v16fp128(<16 x fp128> %x)
  ret <16 x i64> %a
}
declare <16 x i64> @llvm.llrint.v16i64.v16fp128(<16 x fp128>)