llvm/test/CodeGen/AArch64/shuffle-insert-zero.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI


define <2 x double> @testv2f64_0(<2 x double> noundef %vec) {
; CHECK-SD-LABEL: testv2f64_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    mov v0.d[1], xzr
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2f64_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    mov v1.d[1], v1.d[0]
; CHECK-GI-NEXT:    mov v0.d[1], v1.d[1]
; CHECK-GI-NEXT:    ret
entry:
  %vecinit1 = shufflevector <2 x double> %vec, <2 x double> <double poison, double 0.000000e+00>, <2 x i32> <i32 0, i32 3>
  ret <2 x double> %vecinit1
}

define <2 x double> @testv2f64_1(<2 x double> noundef %vec) {
; CHECK-SD-LABEL: testv2f64_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    zip1 v0.2d, v0.2d, v1.2d
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2f64_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    zip1 v0.2d, v0.2d, v1.2d
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <2 x double> <double 0.000000e+00, double poison>, <2 x double> %vec, <2 x i32> <i32 2, i32 0>
  ret <2 x double> %vecins
}

define <4 x float> @testv4f32_0(<4 x float> noundef %vec) {
; CHECK-LABEL: testv4f32_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <4 x float> %vec, <4 x float> <float poison, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
  ret <4 x float> %vecinit3
}

define <4 x float> @testv4f32_1(<4 x float> noundef %vec) {
; CHECK-SD-LABEL: testv4f32_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-SD-NEXT:    mov v0.16b, v1.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4f32_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    dup v1.4s, v1.s[0]
; CHECK-GI-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.16b, v1.16b
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <4 x float> <float 0.000000e+00, float poison, float poison, float poison>, <4 x float> %vec, <4 x i32> <i32 4, i32 0, i32 0, i32 0>
  ret <4 x float> %vecins
}

define <2 x float> @testv2f32_0(<2 x float> noundef %vec) {
; CHECK-SD-LABEL: testv2f32_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v0.s[1], wzr
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2f32_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    mov v1.s[1], v1.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], v1.s[1]
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %vecinit3 = shufflevector <2 x float> %vec, <2 x float> <float poison, float 0.000000e+00>, <2 x i32> <i32 0, i32 3>
  ret <2 x float> %vecinit3
}

define <2 x float> @testv2f32_1(<2 x float> noundef %vec) {
; CHECK-SD-LABEL: testv2f32_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    zip1 v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2f32_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    zip1 v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <2 x float> <float 0.000000e+00, float poison>, <2 x float> %vec, <2 x i32> <i32 2, i32 0>
  ret <2 x float> %vecins
}

define <8 x half> @testv8f16_0(<8 x half> noundef %vec) {
; CHECK-LABEL: testv8f16_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <8 x half> %vec, <8 x half> <half poison, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <8 x half> %vecinit3
}

define <8 x half> @testv8f16_1(<8 x half> noundef %vec) {
; CHECK-SD-LABEL: testv8f16_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    adrp x8, .LCPI7_0
; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
; CHECK-SD-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv8f16_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 def $q31_q0
; CHECK-GI-NEXT:    adrp x8, .LCPI7_0
; CHECK-GI-NEXT:    movi d31, #0000000000000000
; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI7_0]
; CHECK-GI-NEXT:    tbl v0.16b, { v31.16b, v0.16b }, v1.16b
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <8 x half> <half 0.000000e+00, half poison, half poison, half poison, half poison, half poison, half poison, half poison>, <8 x half> %vec, <8 x i32> <i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
  ret <8 x half> %vecins
}

define <4 x half> @testv4f16_0(<4 x half> noundef %vec) {
; CHECK-SD-LABEL: testv4f16_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi d1, #0000000000000000
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-SD-NEXT:    fmov d0, d1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4f16_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi v1.2d, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT:    fmov d0, d1
; CHECK-GI-NEXT:    ret
entry:
  %vecinit3 = shufflevector <4 x half> %vec, <4 x half> <half poison, half 0.000000e+00, half 0.000000e+00, half 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
  ret <4 x half> %vecinit3
}

define <4 x half> @testv4f16_1(<4 x half> noundef %vec) {
; CHECK-SD-LABEL: testv4f16_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-SD-NEXT:    fmov d0, d1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4f16_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    dup v1.4h, v1.h[0]
; CHECK-GI-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT:    fmov d0, d1
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <4 x half> <half 0.000000e+00, half poison, half poison, half poison>, <4 x half> %vec, <4 x i32> <i32 4, i32 0, i32 0, i32 0>
  ret <4 x half> %vecins
}

define <8 x bfloat> @testv8bf16_0(<8 x bfloat> noundef %vec) {
; CHECK-LABEL: testv8bf16_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <8 x bfloat> %vec, <8 x bfloat> <bfloat poison, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <8 x bfloat> %vecinit3
}

define <8 x bfloat> @testv8bf16_1(<8 x bfloat> noundef %vec) {
; CHECK-SD-LABEL: testv8bf16_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    adrp x8, .LCPI11_0
; CHECK-SD-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
; CHECK-SD-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv8bf16_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    // kill: def $q0 killed $q0 def $q31_q0
; CHECK-GI-NEXT:    adrp x8, .LCPI11_0
; CHECK-GI-NEXT:    movi d31, #0000000000000000
; CHECK-GI-NEXT:    ldr q1, [x8, :lo12:.LCPI11_0]
; CHECK-GI-NEXT:    tbl v0.16b, { v31.16b, v0.16b }, v1.16b
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <8 x bfloat> <bfloat 0.000000e+00, bfloat poison, bfloat poison, bfloat poison, bfloat poison, bfloat poison, bfloat poison, bfloat poison>, <8 x bfloat> %vec, <8 x i32> <i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
  ret <8 x bfloat> %vecins
}

define <4 x bfloat> @testv4bf16_0(<4 x bfloat> noundef %vec) {
; CHECK-SD-LABEL: testv4bf16_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi d1, #0000000000000000
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-SD-NEXT:    fmov d0, d1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4bf16_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi v1.2d, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT:    fmov d0, d1
; CHECK-GI-NEXT:    ret
entry:
  %vecinit3 = shufflevector <4 x bfloat> %vec, <4 x bfloat> <bfloat poison, bfloat 0.000000e+00, bfloat 0.000000e+00, bfloat 0.000000e+00>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
  ret <4 x bfloat> %vecinit3
}

define <4 x bfloat> @testv4bf16_1(<4 x bfloat> noundef %vec) {
; CHECK-SD-LABEL: testv4bf16_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-SD-NEXT:    fmov d0, d1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4bf16_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    dup v1.4h, v1.h[0]
; CHECK-GI-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT:    fmov d0, d1
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <4 x bfloat> <bfloat 0.000000e+00, bfloat poison, bfloat poison, bfloat poison>, <4 x bfloat> %vec, <4 x i32> <i32 4, i32 0, i32 0, i32 0>
  ret <4 x bfloat> %vecins
}


define <2 x i64> @testv2i64_0(<2 x i64> noundef %vec) {
; CHECK-SD-LABEL: testv2i64_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    mov v0.d[1], xzr
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2i64_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    mov v1.d[1], xzr
; CHECK-GI-NEXT:    mov v0.d[1], v1.d[1]
; CHECK-GI-NEXT:    ret
entry:
  %vecinit1 = shufflevector <2 x i64> %vec, <2 x i64> <i64 poison, i64 0>, <2 x i32> <i32 0, i32 3>
  ret <2 x i64> %vecinit1
}

define <2 x i64> @testv2i64_1(<2 x i64> noundef %vec) {
; CHECK-SD-LABEL: testv2i64_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    zip1 v0.2d, v0.2d, v1.2d
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2i64_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    zip1 v0.2d, v0.2d, v1.2d
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <2 x i64> <i64 0, i64 poison>, <2 x i64> %vec, <2 x i32> <i32 2, i32 0>
  ret <2 x i64> %vecins
}

define <4 x i32> @testv4i32_0(<4 x i32> noundef %vec) {
; CHECK-LABEL: testv4i32_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <4 x i32> %vec, <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
  ret <4 x i32> %vecinit3
}

define <4 x i32> @testv4i32_1(<4 x i32> noundef %vec) {
; CHECK-SD-LABEL: testv4i32_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-SD-NEXT:    mov v0.16b, v1.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4i32_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    dup v1.4s, v1.s[0]
; CHECK-GI-NEXT:    mov v1.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.16b, v1.16b
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>, <4 x i32> %vec, <4 x i32> <i32 4, i32 0, i32 0, i32 0>
  ret <4 x i32> %vecins
}

define <2 x i32> @testv2i32_0(<2 x i32> noundef %vec) {
; CHECK-SD-LABEL: testv2i32_0:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v0.s[1], wzr
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2i32_0:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    mov v1.s[1], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    mov v0.s[1], v1.s[1]
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %vecinit3 = shufflevector <2 x i32> %vec, <2 x i32> <i32 poison, i32 0>, <2 x i32> <i32 0, i32 3>
  ret <2 x i32> %vecinit3
}

define <2 x i32> @testv2i32_1(<2 x i32> noundef %vec) {
; CHECK-SD-LABEL: testv2i32_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    zip1 v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv2i32_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    zip1 v0.2s, v0.2s, v1.2s
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <2 x i32> <i32 0, i32 poison>, <2 x i32> %vec, <2 x i32> <i32 2, i32 0>
  ret <2 x i32> %vecins
}

define <8 x i16> @testv8i16_0(<8 x i16> noundef %vec) {
; CHECK-LABEL: testv8i16_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <8 x i16> %vec, <8 x i16> <i16 poison, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <8 x i16> %vecinit3
}

define <8 x i16> @testv8i16_1(<8 x i16> noundef %vec) {
; CHECK-LABEL: testv8i16_1:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    adrp x8, .LCPI21_0
; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI21_0]
; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecins = shufflevector <8 x i16> <i16 0, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison, i16 poison>, <8 x i16> %vec, <8 x i32> <i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
  ret <8 x i16> %vecins
}

define <4 x i16> @testv4i16_0(<4 x i16> noundef %vec) {
; CHECK-LABEL: testv4i16_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-NEXT:    fmov d0, d1
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <4 x i16> %vec, <4 x i16> <i16 poison, i16 0, i16 0, i16 0>, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
  ret <4 x i16> %vecinit3
}

define <4 x i16> @testv4i16_1(<4 x i16> noundef %vec) {
; CHECK-SD-LABEL: testv4i16_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    movi v1.2d, #0000000000000000
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-SD-NEXT:    fmov d0, d1
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv4i16_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    dup v1.4h, v1.h[0]
; CHECK-GI-NEXT:    mov v1.h[0], v0.h[0]
; CHECK-GI-NEXT:    fmov d0, d1
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <4 x i16> <i16 0, i16 poison, i16 poison, i16 poison>, <4 x i16> %vec, <4 x i32> <i32 4, i32 0, i32 0, i32 0>
  ret <4 x i16> %vecins
}

define <16 x i8> @testv16i8_0(<16 x i8> noundef %vec) {
; CHECK-LABEL: testv16i8_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    mov v1.b[0], v0.b[0]
; CHECK-NEXT:    mov v0.16b, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <16 x i8> %vec, <16 x i8> <i8 poison, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i32> <i32 0, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
  ret <16 x i8> %vecinit3
}

define <16 x i8> @testv16i8_1(<16 x i8> noundef %vec) {
; CHECK-LABEL: testv16i8_1:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    adrp x8, .LCPI25_0
; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI25_0]
; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-NEXT:    ret
entry:
  %vecins = shufflevector <16 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <16 x i8> %vec, <16 x i32> <i32 16, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
  ret <16 x i8> %vecins
}

define <8 x i8> @testv8i8_0(<8 x i8> noundef %vec) {
; CHECK-LABEL: testv8i8_0:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    movi v1.2d, #0000000000000000
; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-NEXT:    mov v1.b[0], v0.b[0]
; CHECK-NEXT:    fmov d0, d1
; CHECK-NEXT:    ret
entry:
  %vecinit3 = shufflevector <8 x i8> %vec, <8 x i8> <i8 poison, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <8 x i8> %vecinit3
}

define <8 x i8> @testv8i8_1(<8 x i8> noundef %vec) {
; CHECK-SD-LABEL: testv8i8_1:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT:    movi d1, #0xffffffffffffff00
; CHECK-SD-NEXT:    mov v0.d[1], v0.d[0]
; CHECK-SD-NEXT:    tbl v0.8b, { v0.16b }, v1.8b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: testv8i8_1:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    movi d1, #0000000000000000
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 def $q0
; CHECK-GI-NEXT:    adrp x8, .LCPI27_0
; CHECK-GI-NEXT:    mov v0.d[1], v1.d[0]
; CHECK-GI-NEXT:    ldr d1, [x8, :lo12:.LCPI27_0]
; CHECK-GI-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %vecins = shufflevector <8 x i8> <i8 0, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison>, <8 x i8> %vec, <8 x i32> <i32 8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
  ret <8 x i8> %vecins
}