| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 | |
| ; RUN: llc < %s -mtriple=arm64 | FileCheck %s | |
| ; RUN: llc < %s -mtriple=arm64 -global-isel | FileCheck %s | |
| define i32 @testmsws(float %a) { | |
| ; CHECK-LABEL: testmsws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtms w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.floor.f32(float %a) | |
| %conv = fptosi float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testmsxs(float %a) { | |
| ; CHECK-LABEL: testmsxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtms x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.floor.f32(float %a) | |
| %conv = fptosi float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testmswd(double %a) { | |
| ; CHECK-LABEL: testmswd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtms w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.floor.f64(double %a) | |
| %conv = fptosi double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testmsxd(double %a) { | |
| ; CHECK-LABEL: testmsxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtms x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.floor.f64(double %a) | |
| %conv = fptosi double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testmuws(float %a) { | |
| ; CHECK-LABEL: testmuws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtmu w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.floor.f32(float %a) | |
| %conv = fptoui float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testmuxs(float %a) { | |
| ; CHECK-LABEL: testmuxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtmu x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.floor.f32(float %a) | |
| %conv = fptoui float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testmuwd(double %a) { | |
| ; CHECK-LABEL: testmuwd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtmu w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.floor.f64(double %a) | |
| %conv = fptoui double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testmuxd(double %a) { | |
| ; CHECK-LABEL: testmuxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtmu x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.floor.f64(double %a) | |
| %conv = fptoui double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testpsws(float %a) { | |
| ; CHECK-LABEL: testpsws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtps w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.ceil.f32(float %a) | |
| %conv = fptosi float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testpsxs(float %a) { | |
| ; CHECK-LABEL: testpsxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtps x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.ceil.f32(float %a) | |
| %conv = fptosi float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testpswd(double %a) { | |
| ; CHECK-LABEL: testpswd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtps w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.ceil.f64(double %a) | |
| %conv = fptosi double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testpsxd(double %a) { | |
| ; CHECK-LABEL: testpsxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtps x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.ceil.f64(double %a) | |
| %conv = fptosi double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testpuws(float %a) { | |
| ; CHECK-LABEL: testpuws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtpu w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.ceil.f32(float %a) | |
| %conv = fptoui float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testpuxs(float %a) { | |
| ; CHECK-LABEL: testpuxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtpu x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.ceil.f32(float %a) | |
| %conv = fptoui float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testpuwd(double %a) { | |
| ; CHECK-LABEL: testpuwd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtpu w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.ceil.f64(double %a) | |
| %conv = fptoui double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testpuxd(double %a) { | |
| ; CHECK-LABEL: testpuxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtpu x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.ceil.f64(double %a) | |
| %conv = fptoui double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testzsws(float %a) { | |
| ; CHECK-LABEL: testzsws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzs w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.trunc.f32(float %a) | |
| %conv = fptosi float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testzsxs(float %a) { | |
| ; CHECK-LABEL: testzsxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzs x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.trunc.f32(float %a) | |
| %conv = fptosi float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testzswd(double %a) { | |
| ; CHECK-LABEL: testzswd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzs w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.trunc.f64(double %a) | |
| %conv = fptosi double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testzsxd(double %a) { | |
| ; CHECK-LABEL: testzsxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzs x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.trunc.f64(double %a) | |
| %conv = fptosi double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testzuws(float %a) { | |
| ; CHECK-LABEL: testzuws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzu w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.trunc.f32(float %a) | |
| %conv = fptoui float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testzuxs(float %a) { | |
| ; CHECK-LABEL: testzuxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzu x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.trunc.f32(float %a) | |
| %conv = fptoui float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testzuwd(double %a) { | |
| ; CHECK-LABEL: testzuwd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzu w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.trunc.f64(double %a) | |
| %conv = fptoui double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testzuxd(double %a) { | |
| ; CHECK-LABEL: testzuxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtzu x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.trunc.f64(double %a) | |
| %conv = fptoui double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testasws(float %a) { | |
| ; CHECK-LABEL: testasws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtas w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.round.f32(float %a) | |
| %conv = fptosi float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i32 @testnsws(float %a) { | |
| ; CHECK-LABEL: testnsws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtns w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.roundeven.f32(float %a) | |
| %conv = fptosi float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testasxs(float %a) { | |
| ; CHECK-LABEL: testasxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtas x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.round.f32(float %a) | |
| %conv = fptosi float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i64 @testnsxs(float %a) { | |
| ; CHECK-LABEL: testnsxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtns x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.roundeven.f32(float %a) | |
| %conv = fptosi float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testaswd(double %a) { | |
| ; CHECK-LABEL: testaswd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtas w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.round.f64(double %a) | |
| %conv = fptosi double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i32 @testnswd(double %a) { | |
| ; CHECK-LABEL: testnswd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtns w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.roundeven.f64(double %a) | |
| %conv = fptosi double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testasxd(double %a) { | |
| ; CHECK-LABEL: testasxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtas x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.round.f64(double %a) | |
| %conv = fptosi double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i64 @testnsxd(double %a) { | |
| ; CHECK-LABEL: testnsxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtns x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.roundeven.f64(double %a) | |
| %conv = fptosi double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testauws(float %a) { | |
| ; CHECK-LABEL: testauws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtau w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.round.f32(float %a) | |
| %conv = fptoui float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i32 @testnuws(float %a) { | |
| ; CHECK-LABEL: testnuws: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtnu w0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.roundeven.f32(float %a) | |
| %conv = fptoui float %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testauxs(float %a) { | |
| ; CHECK-LABEL: testauxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtau x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.round.f32(float %a) | |
| %conv = fptoui float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i64 @testnuxs(float %a) { | |
| ; CHECK-LABEL: testnuxs: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtnu x0, s0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call float @llvm.roundeven.f32(float %a) | |
| %conv = fptoui float %call to i64 | |
| ret i64 %conv | |
| } | |
| define i32 @testauwd(double %a) { | |
| ; CHECK-LABEL: testauwd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtau w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.round.f64(double %a) | |
| %conv = fptoui double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i32 @testnuwd(double %a) { | |
| ; CHECK-LABEL: testnuwd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtnu w0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.roundeven.f64(double %a) | |
| %conv = fptoui double %call to i32 | |
| ret i32 %conv | |
| } | |
| define i64 @testauxd(double %a) { | |
| ; CHECK-LABEL: testauxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtau x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.round.f64(double %a) | |
| %conv = fptoui double %call to i64 | |
| ret i64 %conv | |
| } | |
| define i64 @testnuxd(double %a) { | |
| ; CHECK-LABEL: testnuxd: | |
| ; CHECK: // %bb.0: // %entry | |
| ; CHECK-NEXT: fcvtnu x0, d0 | |
| ; CHECK-NEXT: ret | |
| entry: | |
| %call = call double @llvm.roundeven.f64(double %a) | |
| %conv = fptoui double %call to i64 | |
| ret i64 %conv | |
| } |