llvm/test/CodeGen/AArch64/fcvt-fixed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,CHECK-NO16,CHECK-SD-NO16,CHECK-SD
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-SD
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-NO16,CHECK-GI-NO16,CHECK-GI
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=+fullfp16 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-GI

; fptoui

define i32 @fcvtzs_f32_i32_7(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptosi float %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzs_f32_i32_32(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = fptosi float %fix to i32
  ret i32 %cvt
}

define float @fcvtzs_f32_i32_7_fpr(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i32_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptosi float %fix to i32
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define float @fcvtzs_f32_i32_32_fpr(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i32_32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = fptosi float %fix to i32
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define i64 @fcvtzs_f32_i64_7(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptosi float %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzs_f32_i64_64(float %flt) {
; CHECK-LABEL: fcvtzs_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, s0, #64
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 18446744073709551616.0
  %cvt = fptosi float %fix to i64
  ret i64 %cvt
}

define i32 @fcvtzs_f64_i32_7(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptosi double %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzs_f64_i32_32(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, d0, #32
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 4294967296.0
  %cvt = fptosi double %fix to i32
  ret i32 %cvt
}

define i64 @fcvtzs_f64_i64_7(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptosi double %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzs_f64_i64_64(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = fptosi double %fix to i64
  ret i64 %cvt
}

define double @fcvtzs_f64_i64_7_fpr(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i64_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptosi double %fix to i64
  %bc = bitcast i64 %cvt to double
  ret double %bc
}

define double @fcvtzs_f64_i64_64_fpr(double %dbl) {
; CHECK-LABEL: fcvtzs_f64_i64_64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = fptosi double %fix to i64
  %bc = bitcast i64 %cvt to double
  ret double %bc
}

define i32 @fcvtzs_f16_i32_7(half %flt) {
; CHECK-NO16-LABEL: fcvtzs_f16_i32_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 128.0
  %cvt = fptosi half %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzs_f16_i32_15(half %flt) {
; CHECK-NO16-LABEL: fcvtzs_f16_i32_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 32768.0
  %cvt = fptosi half %fix to i32
  ret i32 %cvt
}

define i64 @fcvtzs_f16_i64_7(half %flt) {
; CHECK-NO16-LABEL: fcvtzs_f16_i64_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 128.0
  %cvt = fptosi half %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzs_f16_i64_15(half %flt) {
; CHECK-NO16-LABEL: fcvtzs_f16_i64_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs x0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 32768.0
  %cvt = fptosi half %fix to i64
  ret i64 %cvt
}

; fptoui

define i32 @fcvtzu_f32_i32_7(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptoui float %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzu_f32_i32_32(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = fptoui float %fix to i32
  ret i32 %cvt
}

define float @fcvtzu_f32_i32_7_fpr(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i32_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptoui float %fix to i32
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define float @fcvtzu_f32_i32_32_fpr(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i32_32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = fptoui float %fix to i32
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define i64 @fcvtzu_f32_i64_7(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = fptoui float %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzu_f32_i64_64(float %flt) {
; CHECK-LABEL: fcvtzu_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, s0, #64
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 18446744073709551616.0
  %cvt = fptoui float %fix to i64
  ret i64 %cvt
}

define i32 @fcvtzu_f64_i32_7(double %dbl) {
; CHECK-LABEL: fcvtzu_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptoui double %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzu_f64_i32_32(double %dbl) {
; CHECK-LABEL: fcvtzu_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, d0, #32
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 4294967296.0
  %cvt = fptoui double %fix to i32
  ret i32 %cvt
}

define i64 @fcvtzu_f64_i64_7(double %dbl) {
; CHECK-LABEL: fcvtzu_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptoui double %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzu_f64_i64_64(double %dbl) {
; CHECK-LABEL: fcvtzu_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = fptoui double %fix to i64
  ret i64 %cvt
}

define double @fcvtzu_f64_i64_fpr(double %dbl) {
; CHECK-LABEL: fcvtzu_f64_i64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = fptoui double %fix to i64
  %bc = bitcast i64 %cvt to double
  ret double %bc
}

define i32 @fcvtzu_f16_i32_7(half %flt) {
; CHECK-NO16-LABEL: fcvtzu_f16_i32_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 128.0
  %cvt = fptoui half %fix to i32
  ret i32 %cvt
}

define i32 @fcvtzu_f16_i32_15(half %flt) {
; CHECK-NO16-LABEL: fcvtzu_f16_i32_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 32768.0
  %cvt = fptoui half %fix to i32
  ret i32 %cvt
}

define i64 @fcvtzu_f16_i64_7(half %flt) {
; CHECK-NO16-LABEL: fcvtzu_f16_i64_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 128.0
  %cvt = fptoui half %fix to i64
  ret i64 %cvt
}

define i64 @fcvtzu_f16_i64_15(half %flt) {
; CHECK-NO16-LABEL: fcvtzu_f16_i64_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %flt, 32768.0
  %cvt = fptoui half %fix to i64
  ret i64 %cvt
}

; sitofp

define float @scvtf_f32_i32_7(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf s0, w0, #7
; CHECK-NEXT:    ret
  %cvt = sitofp i32 %int to float
  %fix = fdiv float %cvt, 128.0
  ret float %fix
}

define float @scvtf_f32_i32_32(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf s0, w0, #32
; CHECK-NEXT:    ret
  %cvt = sitofp i32 %int to float
  %fix = fdiv float %cvt, 4294967296.0
  ret float %fix
}

define float @scvtf_f32_i64_7(i64 %long) {
; CHECK-LABEL: scvtf_f32_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf s0, x0, #7
; CHECK-NEXT:    ret
  %cvt = sitofp i64 %long to float
  %fix = fdiv float %cvt, 128.0
  ret float %fix
}

define float @scvtf_f32_i64_64(i64 %long) {
; CHECK-LABEL: scvtf_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf s0, x0, #64
; CHECK-NEXT:    ret
  %cvt = sitofp i64 %long to float
  %fix = fdiv float %cvt, 18446744073709551616.0
  ret float %fix
}

define double @scvtf_f64_i32_7(i32 %int) {
; CHECK-LABEL: scvtf_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf d0, w0, #7
; CHECK-NEXT:    ret
  %cvt = sitofp i32 %int to double
  %fix = fdiv double %cvt, 128.0
  ret double %fix
}

define double @scvtf_f64_i32_32(i32 %int) {
; CHECK-LABEL: scvtf_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf d0, w0, #32
; CHECK-NEXT:    ret
  %cvt = sitofp i32 %int to double
  %fix = fdiv double %cvt, 4294967296.0
  ret double %fix
}

define double @scvtf_f64_i64_7(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf d0, x0, #7
; CHECK-NEXT:    ret
  %cvt = sitofp i64 %long to double
  %fix = fdiv double %cvt, 128.0
  ret double %fix
}

define double @scvtf_f64_i64_64(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf d0, x0, #64
; CHECK-NEXT:    ret
  %cvt = sitofp i64 %long to double
  %fix = fdiv double %cvt, 18446744073709551616.0
  ret double %fix
}

define half @scvtf_f16_i32_7(i32 %int) {
; CHECK-SD-NO16-LABEL: scvtf_f16_i32_7:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    scvtf s1, w0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #60, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: scvtf_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    scvtf h0, w0, #7
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i32_7:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    scvtf s1, w0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #67, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = sitofp i32 %int to half
  %fix = fdiv half %cvt, 128.0
  ret half %fix
}

define half @scvtf_f16_i32_15(i32 %int) {
; CHECK-SD-NO16-LABEL: scvtf_f16_i32_15:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    scvtf s1, w0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #56, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: scvtf_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    scvtf h0, w0, #15
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i32_15:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    scvtf s1, w0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #71, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = sitofp i32 %int to half
  %fix = fdiv half %cvt, 32768.0
  ret half %fix
}

define half @scvtf_f16_i64_7(i64 %long) {
; CHECK-SD-NO16-LABEL: scvtf_f16_i64_7:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    scvtf s1, x0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #60, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: scvtf_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    scvtf h0, x0, #7
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i64_7:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    scvtf s1, x0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #67, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = sitofp i64 %long to half
  %fix = fdiv half %cvt, 128.0
  ret half %fix
}

define half @scvtf_f16_i64_15(i64 %long) {
; CHECK-SD-NO16-LABEL: scvtf_f16_i64_15:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    scvtf s1, x0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #56, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: scvtf_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    scvtf h0, x0, #15
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: scvtf_f16_i64_15:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    scvtf s1, x0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #71, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = sitofp i64 %long to half
  %fix = fdiv half %cvt, 32768.0
  ret half %fix
}

; uitofp

define float @ucvtf_f32_i32_7(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf s0, w0, #7
; CHECK-NEXT:    ret
  %cvt = uitofp i32 %int to float
  %fix = fdiv float %cvt, 128.0
  ret float %fix
}

define float @ucvtf_f32_i32_32(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf s0, w0, #32
; CHECK-NEXT:    ret
  %cvt = uitofp i32 %int to float
  %fix = fdiv float %cvt, 4294967296.0
  ret float %fix
}

define float @ucvtf_f32_i64_7(i64 %long) {
; CHECK-LABEL: ucvtf_f32_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf s0, x0, #7
; CHECK-NEXT:    ret
  %cvt = uitofp i64 %long to float
  %fix = fdiv float %cvt, 128.0
  ret float %fix
}

define float @ucvtf_f32_i64_64(i64 %long) {
; CHECK-LABEL: ucvtf_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf s0, x0, #64
; CHECK-NEXT:    ret
  %cvt = uitofp i64 %long to float
  %fix = fdiv float %cvt, 18446744073709551616.0
  ret float %fix
}

define double @ucvtf_f64_i32_7(i32 %int) {
; CHECK-LABEL: ucvtf_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf d0, w0, #7
; CHECK-NEXT:    ret
  %cvt = uitofp i32 %int to double
  %fix = fdiv double %cvt, 128.0
  ret double %fix
}

define double @ucvtf_f64_i32_32(i32 %int) {
; CHECK-LABEL: ucvtf_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf d0, w0, #32
; CHECK-NEXT:    ret
  %cvt = uitofp i32 %int to double
  %fix = fdiv double %cvt, 4294967296.0
  ret double %fix
}

define double @ucvtf_f64_i64_7(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf d0, x0, #7
; CHECK-NEXT:    ret
  %cvt = uitofp i64 %long to double
  %fix = fdiv double %cvt, 128.0
  ret double %fix
}

define double @ucvtf_f64_i64_64(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf d0, x0, #64
; CHECK-NEXT:    ret
  %cvt = uitofp i64 %long to double
  %fix = fdiv double %cvt, 18446744073709551616.0
  ret double %fix
}

define half @ucvtf_f16_i32_7(i32 %int) {
; CHECK-SD-NO16-LABEL: ucvtf_f16_i32_7:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    ucvtf s1, w0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #60, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: ucvtf_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    ucvtf h0, w0, #7
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_7:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    ucvtf s1, w0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #67, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = uitofp i32 %int to half
  %fix = fdiv half %cvt, 128.0
  ret half %fix
}

define half @ucvtf_f16_i32_15(i32 %int) {
; CHECK-SD-NO16-LABEL: ucvtf_f16_i32_15:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    ucvtf s1, w0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #56, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: ucvtf_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    ucvtf h0, w0, #15
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i32_15:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    ucvtf s1, w0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #71, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = uitofp i32 %int to half
  %fix = fdiv half %cvt, 32768.0
  ret half %fix
}

define half @ucvtf_f16_i64_7(i64 %long) {
; CHECK-SD-NO16-LABEL: ucvtf_f16_i64_7:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    ucvtf s1, x0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #60, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: ucvtf_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    ucvtf h0, x0, #7
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_7:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    ucvtf s1, x0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #67, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = uitofp i64 %long to half
  %fix = fdiv half %cvt, 128.0
  ret half %fix
}

define half @ucvtf_f16_i64_15(i64 %long) {
; CHECK-SD-NO16-LABEL: ucvtf_f16_i64_15:
; CHECK-SD-NO16:       // %bb.0:
; CHECK-SD-NO16-NEXT:    ucvtf s1, x0
; CHECK-SD-NO16-NEXT:    movi v0.2s, #56, lsl #24
; CHECK-SD-NO16-NEXT:    fcvt h1, s1
; CHECK-SD-NO16-NEXT:    fcvt s1, h1
; CHECK-SD-NO16-NEXT:    fmul s0, s1, s0
; CHECK-SD-NO16-NEXT:    fcvt h0, s0
; CHECK-SD-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: ucvtf_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    ucvtf h0, x0, #15
; CHECK-FP16-NEXT:    ret
;
; CHECK-GI-NO16-LABEL: ucvtf_f16_i64_15:
; CHECK-GI-NO16:       // %bb.0:
; CHECK-GI-NO16-NEXT:    ucvtf s1, x0
; CHECK-GI-NO16-NEXT:    movi v0.2s, #71, lsl #24
; CHECK-GI-NO16-NEXT:    fcvt h1, s1
; CHECK-GI-NO16-NEXT:    fcvt s1, h1
; CHECK-GI-NO16-NEXT:    fdiv s0, s1, s0
; CHECK-GI-NO16-NEXT:    fcvt h0, s0
; CHECK-GI-NO16-NEXT:    ret
  %cvt = uitofp i64 %long to half
  %fix = fdiv half %cvt, 32768.0
  ret half %fix
}


; fptoui.sat

declare i32 @llvm.fptosi.sat.i32.f32(float)
declare i64 @llvm.fptosi.sat.i64.f32(float)
declare i32 @llvm.fptosi.sat.i32.f64(double)
declare i64 @llvm.fptosi.sat.i64.f64(double)
declare i32 @llvm.fptosi.sat.i32.f16(half)
declare i64 @llvm.fptosi.sat.i64.f16(half)

define i32 @fcvtzs_sat_f32_i32_7(float %flt) {
; CHECK-LABEL: fcvtzs_sat_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
  ret i32 %cvt
}

define i32 @fcvtzs_sat_f32_i32_32(float %flt) {
; CHECK-LABEL: fcvtzs_sat_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
  ret i32 %cvt
}

define float @fcvtzs_sat_f32_i32_7_fpr(float %flt) {
; CHECK-LABEL: fcvtzs_sat_f32_i32_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define float @fcvtzs_sat_f32_i32_32_fpr(float %flt) {
; CHECK-LABEL: fcvtzs_sat_f32_i32_32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f32(float %fix)
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define i64 @fcvtzs_sat_f32_i64_64(float %flt) {
; CHECK-LABEL: fcvtzs_sat_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, s0, #64
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 18446744073709551616.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f32(float %fix)
  ret i64 %cvt
}

define i32 @fcvtzs_sat_f64_i32_7(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
  ret i32 %cvt
}

define i32 @fcvtzs_sat_f64_i32_32(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, d0, #32
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 4294967296.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f64(double %fix)
  ret i32 %cvt
}

define i64 @fcvtzs_sat_f64_i64_7(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
  ret i64 %cvt
}

define i64 @fcvtzs_sat_f64_i64_64(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs x0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
  ret i64 %cvt
}

define double @fcvtzs_sat_f64_i64_7_fpr(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i64_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
  %bc = bitcast i64 %cvt to double
  ret double %bc
}

define double @fcvtzs_sat_f64_i64_64_fpr(double %dbl) {
; CHECK-LABEL: fcvtzs_sat_f64_i64_64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f64(double %fix)
  %bc = bitcast i64 %cvt to double
  ret double %bc
}


define i32 @fcvtzs_sat_f16_i32_7(half %dbl) {
; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs w0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 128.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
  ret i32 %cvt
}

define i32 @fcvtzs_sat_f16_i32_15(half %dbl) {
; CHECK-NO16-LABEL: fcvtzs_sat_f16_i32_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_sat_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs w0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 32768.0
  %cvt = call i32 @llvm.fptosi.sat.i32.f16(half %fix)
  ret i32 %cvt
}

define i64 @fcvtzs_sat_f16_i64_7(half %dbl) {
; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs x0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 128.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
  ret i64 %cvt
}

define i64 @fcvtzs_sat_f16_i64_15(half %dbl) {
; CHECK-NO16-LABEL: fcvtzs_sat_f16_i64_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzs x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzs_sat_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzs x0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 32768.0
  %cvt = call i64 @llvm.fptosi.sat.i64.f16(half %fix)
  ret i64 %cvt
}

; fptoui

declare i32 @llvm.fptoui.sat.i32.f32(float)
declare i64 @llvm.fptoui.sat.i64.f32(float)
declare i32 @llvm.fptoui.sat.i32.f64(double)
declare i64 @llvm.fptoui.sat.i64.f64(double)
declare i32 @llvm.fptoui.sat.i32.f16(half)
declare i64 @llvm.fptoui.sat.i64.f16(half)

define i32 @fcvtzu_sat_f32_i32_7(float %flt) {
; CHECK-LABEL: fcvtzu_sat_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
  ret i32 %cvt
}

define i32 @fcvtzu_sat_f32_i32_32(float %flt) {
; CHECK-LABEL: fcvtzu_sat_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
  ret i32 %cvt
}

define float @fcvtzu_sat_f32_i32_7_fpr(float %flt) {
; CHECK-LABEL: fcvtzu_sat_f32_i32_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #7
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 128.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define float @fcvtzu_sat_f32_i32_32_fpr(float %flt) {
; CHECK-LABEL: fcvtzu_sat_f32_i32_32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #32
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 4294967296.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f32(float %fix)
  %bc = bitcast i32 %cvt to float
  ret float %bc
}

define i64 @fcvtzu_sat_f32_i64_64(float %flt) {
; CHECK-LABEL: fcvtzu_sat_f32_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, s0, #64
; CHECK-NEXT:    ret
  %fix = fmul float %flt, 18446744073709551616.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f32(float %fix)
  ret i64 %cvt
}

define i32 @fcvtzu_sat_f64_i32_7(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
  ret i32 %cvt
}

define i32 @fcvtzu_sat_f64_i32_32(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, d0, #32
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 4294967296.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f64(double %fix)
  ret i32 %cvt
}

define i64 @fcvtzu_sat_f64_i64_7(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i64_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
  ret i64 %cvt
}

define i64 @fcvtzu_sat_f64_i64_64(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i64_64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu x0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
  ret i64 %cvt
}

define double @fcvtzu_sat_f64_i64_7_fpr(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i64_7_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0, #7
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 128.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
  %bc = bitcast i64 %cvt to double
  ret double %bc
}

define double @fcvtzu_sat_f64_i64_64_fpr(double %dbl) {
; CHECK-LABEL: fcvtzu_sat_f64_i64_64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0, #64
; CHECK-NEXT:    ret
  %fix = fmul double %dbl, 18446744073709551616.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f64(double %fix)
  %bc = bitcast i64 %cvt to double
  ret double %bc
}


define i32 @fcvtzu_sat_f16_i32_7(half %dbl) {
; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu w0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 128.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
  ret i32 %cvt
}

define i32 @fcvtzu_sat_f16_i32_15(half %dbl) {
; CHECK-NO16-LABEL: fcvtzu_sat_f16_i32_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu w0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i32_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu w0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 32768.0
  %cvt = call i32 @llvm.fptoui.sat.i32.f16(half %fix)
  ret i32 %cvt
}

define i64 @fcvtzu_sat_f16_i64_7(half %dbl) {
; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_7:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #67, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_7:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu x0, h0, #7
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 128.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
  ret i64 %cvt
}

define i64 @fcvtzu_sat_f16_i64_15(half %dbl) {
; CHECK-NO16-LABEL: fcvtzu_sat_f16_i64_15:
; CHECK-NO16:       // %bb.0:
; CHECK-NO16-NEXT:    movi v1.2s, #71, lsl #24
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fmul s0, s0, s1
; CHECK-NO16-NEXT:    fcvt h0, s0
; CHECK-NO16-NEXT:    fcvt s0, h0
; CHECK-NO16-NEXT:    fcvtzu x0, s0
; CHECK-NO16-NEXT:    ret
;
; CHECK-FP16-LABEL: fcvtzu_sat_f16_i64_15:
; CHECK-FP16:       // %bb.0:
; CHECK-FP16-NEXT:    fcvtzu x0, h0, #15
; CHECK-FP16-NEXT:    ret
  %fix = fmul half %dbl, 32768.0
  %cvt = call i64 @llvm.fptoui.sat.i64.f16(half %fix)
  ret i64 %cvt
}

define i32 @neon_fcvtzs_f32_i32_7(float %a) {
; CHECK-LABEL: neon_fcvtzs_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #7
; CHECK-NEXT:    ret
  %mul = fmul float %a, 128.0
  %r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
  ret i32 %r
}

define i32 @neon_fcvtzs_f32_i32_32(float %a) {
; CHECK-LABEL: neon_fcvtzs_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs w0, s0, #32
; CHECK-NEXT:    ret
  %mul = fmul float %a, 4294967296.0
  %r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
  ret i32 %r
}

define float @neon_fcvtzs_f32_i32_7_bitcast(float %a) {
; CHECK-LABEL: neon_fcvtzs_f32_i32_7_bitcast:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #7
; CHECK-NEXT:    ret
  %mul = fmul float %a, 128.0
  %r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
  %bc = bitcast i32 %r to float
  ret float %bc
}

define float @neon_fcvtzs_f32_i32_32_bitcast(float %a) {
; CHECK-LABEL: neon_fcvtzs_f32_i32_32_bitcast:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0, #32
; CHECK-NEXT:    ret
  %mul = fmul float %a, 4294967296.0
  %r = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %mul)
  %bc = bitcast i32 %r to float
  ret float %bc
}

define i32 @neon_fcvtzu_f32_i32_7(float %a) {
; CHECK-LABEL: neon_fcvtzu_f32_i32_7:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #7
; CHECK-NEXT:    ret
  %mul = fmul float %a, 128.0
  %r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
  ret i32 %r
}

define i32 @neon_fcvtzu_f32_i32_32(float %a) {
; CHECK-LABEL: neon_fcvtzu_f32_i32_32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu w0, s0, #32
; CHECK-NEXT:    ret
  %mul = fmul float %a, 4294967296.0
  %r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
  ret i32 %r
}

define float @neon_fcvtzu_f32_i32_7_bitcast(float %a) {
; CHECK-LABEL: neon_fcvtzu_f32_i32_7_bitcast:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #7
; CHECK-NEXT:    ret
  %mul = fmul float %a, 128.0
  %r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
  %bc = bitcast i32 %r to float
  ret float %bc
}

define float @neon_fcvtzu_f32_i32_32_bitcast(float %a) {
; CHECK-LABEL: neon_fcvtzu_f32_i32_32_bitcast:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0, #32
; CHECK-NEXT:    ret
  %mul = fmul float %a, 4294967296.0
  %r = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %mul)
  %bc = bitcast i32 %r to float
  ret float %bc
}


define float @scvtf_f32_i32_3_input_in_fpr(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_3_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    scvtf s0, s0, #3
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %int, i32 %int)
  %cvt = sitofp i32 %sum to float
  %fix = fdiv float %cvt, 8.0
  ret float %fix
}

define float @scvtf_f32_i32_5_fmul_input_in_fpr(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_5_fmul_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    scvtf s0, s0, #5
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %int, i32 %int)
  %cvt = sitofp i32 %sum to float
  %fix = fmul float %cvt, 0x1.0p-5
  ret float %fix
}

define double @scvtf_f64_i64_6_input_in_fpr(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_6_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    scvtf d0, d0, #6
; CHECK-NEXT:    ret

  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %long, i64 %long)
  %cvt = sitofp i64 %sum to double
  %fix = fdiv double %cvt, 64.0
  ret double %fix
}

define double @scvtf_f64_i64_9_fmul_input_in_fpr(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_9_fmul_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    scvtf d0, d0, #9
; CHECK-NEXT:    ret
  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %long, i64 %long)
  %cvt = sitofp i64 %sum to double
  %fix = fmul double %cvt, 0x1.0p-9
  ret double %fix
}

define float @ucvtf_f32_i32_3_input_in_fpr(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_3_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    ucvtf s0, s0, #3
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %int, i32 %int)
  %cvt = uitofp i32 %sum to float
  %fix = fdiv float %cvt, 8.0
  ret float %fix
}

define float @ucvtf_f32_i32_5_fmul_input_in_fpr(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_5_fmul_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    ucvtf s0, s0, #5
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %int, i32 %int)
  %cvt = uitofp i32 %sum to float
  %fix = fmul float %cvt, 0x1.0p-5
  ret float %fix
}

define double @ucvtf_f64_i64_6_input_in_fpr(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_6_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    ucvtf d0, d0, #6
; CHECK-NEXT:    ret
  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %long, i64 %long)
  %cvt = uitofp i64 %sum to double
  %fix = fdiv double %cvt, 64.0
  ret double %fix
}

define double @ucvtf_f64_i64_9_fmul_input_in_fpr(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_9_fmul_input_in_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    ucvtf d0, d0, #9
; CHECK-NEXT:    ret
  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %long, i64 %long)
  %cvt = uitofp i64 %sum to double
  %fix = fmul double %cvt, 0x1.0p-9
  ret double %fix
}

define float @scvtf_f32_i32_3_input_in_gpr(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_3_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add w8, w0, w0
; CHECK-NEXT:    scvtf s0, w8, #3
; CHECK-NEXT:    ret
  %sum = add i32 %int, %int
  %cvt = sitofp i32 %sum to float
  %fix = fdiv float %cvt, 8.0
  ret float %fix
}

define float @scvtf_f32_i32_5_fmul_input_in_gpr(i32 %int) {
; CHECK-LABEL: scvtf_f32_i32_5_fmul_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add w8, w0, w0
; CHECK-NEXT:    scvtf s0, w8, #5
; CHECK-NEXT:    ret
  %sum = add i32 %int, %int
  %cvt = sitofp i32 %sum to float
  %fix = fmul float %cvt, 0x1.0p-5
  ret float %fix
}

define double @scvtf_f64_i64_6_input_in_gpr(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_6_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add x8, x0, x0
; CHECK-NEXT:    scvtf d0, x8, #6
; CHECK-NEXT:    ret
  %sum = add i64 %long, %long
  %cvt = sitofp i64 %sum to double
  %fix = fdiv double %cvt, 64.0
  ret double %fix
}

define double @scvtf_f64_i64_9_fmul_input_in_gpr(i64 %long) {
; CHECK-LABEL: scvtf_f64_i64_9_fmul_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add x8, x0, x0
; CHECK-NEXT:    scvtf d0, x8, #9
; CHECK-NEXT:    ret
  %sum = add i64 %long, %long
  %cvt = sitofp i64 %sum to double
  %fix = fmul double %cvt, 0x1.0p-9
  ret double %fix
}

define float @ucvtf_f32_i32_3_input_in_gpr(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_3_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add w8, w0, w0
; CHECK-NEXT:    ucvtf s0, w8, #3
; CHECK-NEXT:    ret
  %sum = add i32 %int, %int
  %cvt = uitofp i32 %sum to float
  %fix = fdiv float %cvt, 8.0
  ret float %fix
}

define float @ucvtf_f32_i32_5_fmul_input_in_gpr(i32 %int) {
; CHECK-LABEL: ucvtf_f32_i32_5_fmul_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add w8, w0, w0
; CHECK-NEXT:    ucvtf s0, w8, #5
; CHECK-NEXT:    ret
  %sum = add i32 %int, %int
  %cvt = uitofp i32 %sum to float
  %fix = fmul float %cvt, 0x1.0p-5
  ret float %fix
}

define double @ucvtf_f64_i64_6_input_in_gpr(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_6_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add x8, x0, x0
; CHECK-NEXT:    ucvtf d0, x8, #6
; CHECK-NEXT:    ret
  %sum = add i64 %long, %long
  %cvt = uitofp i64 %sum to double
  %fix = fdiv double %cvt, 64.0
  ret double %fix
}

define double @ucvtf_f64_i64_9_fmul_input_in_gpr(i64 %long) {
; CHECK-LABEL: ucvtf_f64_i64_9_fmul_input_in_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    add x8, x0, x0
; CHECK-NEXT:    ucvtf d0, x8, #9
; CHECK-NEXT:    ret
  %sum = add i64 %long, %long
  %cvt = uitofp i64 %sum to double
  %fix = fmul double %cvt, 0x1.0p-9
  ret double %fix
}
define float @neon_vcvtfxu2fp_i32_f32_gpr(i32 %a) {
; CHECK-LABEL: neon_vcvtfxu2fp_i32_f32_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf s0, w0, #16
; CHECK-NEXT:    ret
  %cvt = tail call float @llvm.aarch64.neon.vcvtfxu2fp.i32.f32(i32 %a, i32 16)
  ret float %cvt
}

define float @neon_vcvtfxu2fp_i32_f32_fpr(i32 %a) {
; CHECK-LABEL: neon_vcvtfxu2fp_i32_f32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    ucvtf s0, s0, #16
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %a, i32 %a)
  %cvt = tail call float @llvm.aarch64.neon.vcvtfxu2fp.i32.f32(i32 %sum, i32 16)
  ret float %cvt
}

define float @neon_vcvtfxs2fp_i32_f32_gpr(i32 %a) {
; CHECK-LABEL: neon_vcvtfxs2fp_i32_f32_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf s0, w0, #16
; CHECK-NEXT:    ret
  %cvt = call float @llvm.aarch64.neon.vcvtfxs2fp.i32.f32(i32 %a, i32 16)
  ret float %cvt
}

define double @neon_vcvtfxs2fp_i64_f64_gpr(i64 %a) {
; CHECK-LABEL: neon_vcvtfxs2fp_i64_f64_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    scvtf d0, x0, #32
; CHECK-NEXT:    ret
  %cvt = call double @llvm.aarch64.neon.vcvtfxs2fp.i64.f64(i64 %a, i32 32)
  ret double %cvt
}

define double @neon_vcvtfxu2fp_i64_f64_gpr(i64 %a) {
; CHECK-LABEL: neon_vcvtfxu2fp_i64_f64_gpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ucvtf d0, x0, #32
; CHECK-NEXT:    ret
  %cvt = call double @llvm.aarch64.neon.vcvtfxu2fp.i64.f64(i64 %a, i32 32)
  ret double %cvt
}

define float @neon_vcvtfxs2fp_i32_f32_fpr(i32 %a) {
; CHECK-LABEL: neon_vcvtfxs2fp_i32_f32_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov s0, w0
; CHECK-NEXT:    usqadd s0, s0
; CHECK-NEXT:    scvtf s0, s0, #16
; CHECK-NEXT:    ret
  %sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %a, i32 %a)
  %cvt = call float @llvm.aarch64.neon.vcvtfxs2fp.i32.f32(i32 %sum, i32 16)
  ret float %cvt
}

define double @neon_vcvtfxs2fp_i64_f64_fpr(i64 %a) {
; CHECK-LABEL: neon_vcvtfxs2fp_i64_f64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    scvtf d0, d0, #32
; CHECK-NEXT:    ret
  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %a, i64 %a)
  %cvt = call double @llvm.aarch64.neon.vcvtfxs2fp.i64.f64(i64 %sum, i32 32)
  ret double %cvt
}

define double @neon_vcvtfxu2fp_i64_f64_fpr(i64 %a) {
; CHECK-LABEL: neon_vcvtfxu2fp_i64_f64_fpr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmov d0, x0
; CHECK-NEXT:    usqadd d0, d0
; CHECK-NEXT:    ucvtf d0, d0, #32
; CHECK-NEXT:    ret
  %sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %a, i64 %a)
  %cvt = call double @llvm.aarch64.neon.vcvtfxu2fp.i64.f64(i64 %sum, i32 32)
  ret double %cvt
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK-GI: {{.*}}
; CHECK-SD: {{.*}}