| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 |
| ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \ |
| ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 |
| |
| declare <vscale x 8 x i7> @llvm.vp.smin.nxv8i7(<vscale x 8 x i7>, <vscale x 8 x i7>, <vscale x 8 x i1>, i32) |
| |
| define <vscale x 8 x i7> @vmin_vx_nxv8i7(<vscale x 8 x i7> %a, i7 signext %b, <vscale x 8 x i1> %mask, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i7: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma |
| ; CHECK-NEXT: vadd.vv v8, v8, v8 |
| ; CHECK-NEXT: vsra.vi v8, v8, 1 |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i7> poison, i7 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i7> %elt.head, <vscale x 8 x i7> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i7> @llvm.vp.smin.nxv8i7(<vscale x 8 x i7> %a, <vscale x 8 x i7> %vb, <vscale x 8 x i1> %mask, i32 %evl) |
| ret <vscale x 8 x i7> %v |
| } |
| |
| declare <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8>, <vscale x 1 x i8>, <vscale x 1 x i1>, i32) |
| |
| define <vscale x 1 x i8> @vmin_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i8> %v |
| } |
| |
| define <vscale x 1 x i8> @vmin_vv_nxv1i8_unmasked(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i8> %v |
| } |
| |
| define <vscale x 1 x i8> @vmin_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i8> %v |
| } |
| |
| define <vscale x 1 x i8> @vmin_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i8_commute: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8> %vb, <vscale x 1 x i8> %va, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i8> %v |
| } |
| |
| define <vscale x 1 x i8> @vmin_vx_nxv1i8_unmasked(<vscale x 1 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i8> @llvm.vp.smin.nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i8> %v |
| } |
| |
| declare <vscale x 2 x i8> @llvm.vp.smin.nxv2i8(<vscale x 2 x i8>, <vscale x 2 x i8>, <vscale x 2 x i1>, i32) |
| |
| define <vscale x 2 x i8> @vmin_vv_nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 2 x i8> @llvm.vp.smin.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i8> %v |
| } |
| |
| define <vscale x 2 x i8> @vmin_vv_nxv2i8_unmasked(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i8> @llvm.vp.smin.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i8> %v |
| } |
| |
| define <vscale x 2 x i8> @vmin_vx_nxv2i8(<vscale x 2 x i8> %va, i8 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i8> @llvm.vp.smin.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i8> %v |
| } |
| |
| define <vscale x 2 x i8> @vmin_vx_nxv2i8_unmasked(<vscale x 2 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i8> @llvm.vp.smin.nxv2i8(<vscale x 2 x i8> %va, <vscale x 2 x i8> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i8> %v |
| } |
| |
| declare <vscale x 3 x i8> @llvm.vp.smin.nxv3i8(<vscale x 3 x i8>, <vscale x 3 x i8>, <vscale x 3 x i1>, i32) |
| |
| define <vscale x 3 x i8> @vmin_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv3i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 3 x i8> @llvm.vp.smin.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl) |
| ret <vscale x 3 x i8> %v |
| } |
| |
| define <vscale x 3 x i8> @vmin_vv_nxv3i8_unmasked(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv3i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 3 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 3 x i1> %head, <vscale x 3 x i1> poison, <vscale x 3 x i32> zeroinitializer |
| %v = call <vscale x 3 x i8> @llvm.vp.smin.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %b, <vscale x 3 x i1> %m, i32 %evl) |
| ret <vscale x 3 x i8> %v |
| } |
| |
| define <vscale x 3 x i8> @vmin_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b, <vscale x 3 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv3i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer |
| %v = call <vscale x 3 x i8> @llvm.vp.smin.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl) |
| ret <vscale x 3 x i8> %v |
| } |
| |
| define <vscale x 3 x i8> @vmin_vx_nxv3i8_unmasked(<vscale x 3 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv3i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 3 x i8> %elt.head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer |
| %head = insertelement <vscale x 3 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 3 x i1> %head, <vscale x 3 x i1> poison, <vscale x 3 x i32> zeroinitializer |
| %v = call <vscale x 3 x i8> @llvm.vp.smin.nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb, <vscale x 3 x i1> %m, i32 %evl) |
| ret <vscale x 3 x i8> %v |
| } |
| |
| declare <vscale x 4 x i8> @llvm.vp.smin.nxv4i8(<vscale x 4 x i8>, <vscale x 4 x i8>, <vscale x 4 x i1>, i32) |
| |
| define <vscale x 4 x i8> @vmin_vv_nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 4 x i8> @llvm.vp.smin.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i8> %v |
| } |
| |
| define <vscale x 4 x i8> @vmin_vv_nxv4i8_unmasked(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i8> @llvm.vp.smin.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i8> %v |
| } |
| |
| define <vscale x 4 x i8> @vmin_vx_nxv4i8(<vscale x 4 x i8> %va, i8 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i8> @llvm.vp.smin.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i8> %v |
| } |
| |
| define <vscale x 4 x i8> @vmin_vx_nxv4i8_unmasked(<vscale x 4 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i8> @llvm.vp.smin.nxv4i8(<vscale x 4 x i8> %va, <vscale x 4 x i8> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i8> %v |
| } |
| |
| declare <vscale x 8 x i8> @llvm.vp.smin.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i1>, i32) |
| |
| define <vscale x 8 x i8> @vmin_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 8 x i8> @llvm.vp.smin.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i8> %v |
| } |
| |
| define <vscale x 8 x i8> @vmin_vv_nxv8i8_unmasked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i8> @llvm.vp.smin.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i8> %v |
| } |
| |
| define <vscale x 8 x i8> @vmin_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i8> @llvm.vp.smin.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i8> %v |
| } |
| |
| define <vscale x 8 x i8> @vmin_vx_nxv8i8_unmasked(<vscale x 8 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i8> @llvm.vp.smin.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i8> %v |
| } |
| |
| declare <vscale x 16 x i8> @llvm.vp.smin.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i1>, i32) |
| |
| define <vscale x 16 x i8> @vmin_vv_nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 16 x i8> @llvm.vp.smin.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i8> %v |
| } |
| |
| define <vscale x 16 x i8> @vmin_vv_nxv16i8_unmasked(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i8> @llvm.vp.smin.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i8> %v |
| } |
| |
| define <vscale x 16 x i8> @vmin_vx_nxv16i8(<vscale x 16 x i8> %va, i8 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i8> @llvm.vp.smin.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i8> %v |
| } |
| |
| define <vscale x 16 x i8> @vmin_vx_nxv16i8_unmasked(<vscale x 16 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i8> @llvm.vp.smin.nxv16i8(<vscale x 16 x i8> %va, <vscale x 16 x i8> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i8> %v |
| } |
| |
| declare <vscale x 32 x i8> @llvm.vp.smin.nxv32i8(<vscale x 32 x i8>, <vscale x 32 x i8>, <vscale x 32 x i1>, i32) |
| |
| define <vscale x 32 x i8> @vmin_vv_nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv32i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 32 x i8> @llvm.vp.smin.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i8> %v |
| } |
| |
| define <vscale x 32 x i8> @vmin_vv_nxv32i8_unmasked(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv32i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i8> @llvm.vp.smin.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %b, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i8> %v |
| } |
| |
| define <vscale x 32 x i8> @vmin_vx_nxv32i8(<vscale x 32 x i8> %va, i8 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i8> @llvm.vp.smin.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i8> %v |
| } |
| |
| define <vscale x 32 x i8> @vmin_vx_nxv32i8_unmasked(<vscale x 32 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer |
| %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i8> @llvm.vp.smin.nxv32i8(<vscale x 32 x i8> %va, <vscale x 32 x i8> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i8> %v |
| } |
| |
| declare <vscale x 64 x i8> @llvm.vp.smin.nxv64i8(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i1>, i32) |
| |
| define <vscale x 64 x i8> @vmin_vv_nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv64i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 64 x i8> @llvm.vp.smin.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl) |
| ret <vscale x 64 x i8> %v |
| } |
| |
| define <vscale x 64 x i8> @vmin_vv_nxv64i8_unmasked(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv64i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer |
| %v = call <vscale x 64 x i8> @llvm.vp.smin.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %b, <vscale x 64 x i1> %m, i32 %evl) |
| ret <vscale x 64 x i8> %v |
| } |
| |
| define <vscale x 64 x i8> @vmin_vx_nxv64i8(<vscale x 64 x i8> %va, i8 %b, <vscale x 64 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv64i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer |
| %v = call <vscale x 64 x i8> @llvm.vp.smin.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl) |
| ret <vscale x 64 x i8> %v |
| } |
| |
| define <vscale x 64 x i8> @vmin_vx_nxv64i8_unmasked(<vscale x 64 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv64i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer |
| %head = insertelement <vscale x 64 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 64 x i1> %head, <vscale x 64 x i1> poison, <vscale x 64 x i32> zeroinitializer |
| %v = call <vscale x 64 x i8> @llvm.vp.smin.nxv64i8(<vscale x 64 x i8> %va, <vscale x 64 x i8> %vb, <vscale x 64 x i1> %m, i32 %evl) |
| ret <vscale x 64 x i8> %v |
| } |
| |
| ; Test that split-legalization works when the mask itself needs splitting. |
| |
| declare <vscale x 128 x i8> @llvm.vp.smin.nxv128i8(<vscale x 128 x i8>, <vscale x 128 x i8>, <vscale x 128 x i1>, i32) |
| |
| define <vscale x 128 x i8> @vmin_vx_nxv128i8(<vscale x 128 x i8> %va, i8 %b, <vscale x 128 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv128i8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v24, v0 |
| ; CHECK-NEXT: vsetvli a3, zero, e8, m8, ta, ma |
| ; CHECK-NEXT: vlm.v v0, (a1) |
| ; CHECK-NEXT: csrr a1, vlenb |
| ; CHECK-NEXT: slli a1, a1, 3 |
| ; CHECK-NEXT: sub a3, a2, a1 |
| ; CHECK-NEXT: sltu a4, a2, a3 |
| ; CHECK-NEXT: addi a4, a4, -1 |
| ; CHECK-NEXT: and a3, a4, a3 |
| ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t |
| ; CHECK-NEXT: bltu a2, a1, .LBB34_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: mv a2, a1 |
| ; CHECK-NEXT: .LBB34_2: |
| ; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma |
| ; CHECK-NEXT: vmv1r.v v0, v24 |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 128 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 128 x i8> %elt.head, <vscale x 128 x i8> poison, <vscale x 128 x i32> zeroinitializer |
| %v = call <vscale x 128 x i8> @llvm.vp.smin.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 %evl) |
| ret <vscale x 128 x i8> %v |
| } |
| |
| define <vscale x 128 x i8> @vmin_vx_nxv128i8_unmasked(<vscale x 128 x i8> %va, i8 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv128i8_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: csrr a2, vlenb |
| ; CHECK-NEXT: slli a2, a2, 3 |
| ; CHECK-NEXT: sub a3, a1, a2 |
| ; CHECK-NEXT: sltu a4, a1, a3 |
| ; CHECK-NEXT: addi a4, a4, -1 |
| ; CHECK-NEXT: and a3, a4, a3 |
| ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v16, v16, a0 |
| ; CHECK-NEXT: bltu a1, a2, .LBB35_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: mv a1, a2 |
| ; CHECK-NEXT: .LBB35_2: |
| ; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 128 x i8> poison, i8 %b, i32 0 |
| %vb = shufflevector <vscale x 128 x i8> %elt.head, <vscale x 128 x i8> poison, <vscale x 128 x i32> zeroinitializer |
| %head = insertelement <vscale x 128 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 128 x i1> %head, <vscale x 128 x i1> poison, <vscale x 128 x i32> zeroinitializer |
| %v = call <vscale x 128 x i8> @llvm.vp.smin.nxv128i8(<vscale x 128 x i8> %va, <vscale x 128 x i8> %vb, <vscale x 128 x i1> %m, i32 %evl) |
| ret <vscale x 128 x i8> %v |
| } |
| |
| declare <vscale x 1 x i16> @llvm.vp.smin.nxv1i16(<vscale x 1 x i16>, <vscale x 1 x i16>, <vscale x 1 x i1>, i32) |
| |
| define <vscale x 1 x i16> @vmin_vv_nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 1 x i16> @llvm.vp.smin.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i16> %v |
| } |
| |
| define <vscale x 1 x i16> @vmin_vv_nxv1i16_unmasked(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i16> @llvm.vp.smin.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i16> %v |
| } |
| |
| define <vscale x 1 x i16> @vmin_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i16> @llvm.vp.smin.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i16> %v |
| } |
| |
| define <vscale x 1 x i16> @vmin_vx_nxv1i16_unmasked(<vscale x 1 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i16> @llvm.vp.smin.nxv1i16(<vscale x 1 x i16> %va, <vscale x 1 x i16> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i16> %v |
| } |
| |
| declare <vscale x 2 x i16> @llvm.vp.smin.nxv2i16(<vscale x 2 x i16>, <vscale x 2 x i16>, <vscale x 2 x i1>, i32) |
| |
| define <vscale x 2 x i16> @vmin_vv_nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 2 x i16> @llvm.vp.smin.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i16> %v |
| } |
| |
| define <vscale x 2 x i16> @vmin_vv_nxv2i16_unmasked(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i16> @llvm.vp.smin.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i16> %v |
| } |
| |
| define <vscale x 2 x i16> @vmin_vx_nxv2i16(<vscale x 2 x i16> %va, i16 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i16> @llvm.vp.smin.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i16> %v |
| } |
| |
| define <vscale x 2 x i16> @vmin_vx_nxv2i16_unmasked(<vscale x 2 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i16> @llvm.vp.smin.nxv2i16(<vscale x 2 x i16> %va, <vscale x 2 x i16> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i16> %v |
| } |
| |
| declare <vscale x 4 x i16> @llvm.vp.smin.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, <vscale x 4 x i1>, i32) |
| |
| define <vscale x 4 x i16> @vmin_vv_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 4 x i16> @llvm.vp.smin.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i16> %v |
| } |
| |
| define <vscale x 4 x i16> @vmin_vv_nxv4i16_unmasked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i16> @llvm.vp.smin.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i16> %v |
| } |
| |
| define <vscale x 4 x i16> @vmin_vx_nxv4i16(<vscale x 4 x i16> %va, i16 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i16> @llvm.vp.smin.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i16> %v |
| } |
| |
| define <vscale x 4 x i16> @vmin_vx_nxv4i16_unmasked(<vscale x 4 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i16> @llvm.vp.smin.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i16> %v |
| } |
| |
| declare <vscale x 8 x i16> @llvm.vp.smin.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i1>, i32) |
| |
| define <vscale x 8 x i16> @vmin_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 8 x i16> @llvm.vp.smin.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i16> %v |
| } |
| |
| define <vscale x 8 x i16> @vmin_vv_nxv8i16_unmasked(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i16> @llvm.vp.smin.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i16> %v |
| } |
| |
| define <vscale x 8 x i16> @vmin_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i16> @llvm.vp.smin.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i16> %v |
| } |
| |
| define <vscale x 8 x i16> @vmin_vx_nxv8i16_unmasked(<vscale x 8 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i16> @llvm.vp.smin.nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i16> %v |
| } |
| |
| declare <vscale x 16 x i16> @llvm.vp.smin.nxv16i16(<vscale x 16 x i16>, <vscale x 16 x i16>, <vscale x 16 x i1>, i32) |
| |
| define <vscale x 16 x i16> @vmin_vv_nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 16 x i16> @llvm.vp.smin.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i16> %v |
| } |
| |
| define <vscale x 16 x i16> @vmin_vv_nxv16i16_unmasked(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i16> @llvm.vp.smin.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i16> %v |
| } |
| |
| define <vscale x 16 x i16> @vmin_vx_nxv16i16(<vscale x 16 x i16> %va, i16 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i16> @llvm.vp.smin.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i16> %v |
| } |
| |
| define <vscale x 16 x i16> @vmin_vx_nxv16i16_unmasked(<vscale x 16 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i16> @llvm.vp.smin.nxv16i16(<vscale x 16 x i16> %va, <vscale x 16 x i16> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i16> %v |
| } |
| |
| declare <vscale x 32 x i16> @llvm.vp.smin.nxv32i16(<vscale x 32 x i16>, <vscale x 32 x i16>, <vscale x 32 x i1>, i32) |
| |
| define <vscale x 32 x i16> @vmin_vv_nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv32i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 32 x i16> @llvm.vp.smin.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i16> %v |
| } |
| |
| define <vscale x 32 x i16> @vmin_vv_nxv32i16_unmasked(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv32i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i16> @llvm.vp.smin.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %b, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i16> %v |
| } |
| |
| define <vscale x 32 x i16> @vmin_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i16: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i16> @llvm.vp.smin.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i16> %v |
| } |
| |
| define <vscale x 32 x i16> @vmin_vx_nxv32i16_unmasked(<vscale x 32 x i16> %va, i16 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i16_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer |
| %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i16> @llvm.vp.smin.nxv32i16(<vscale x 32 x i16> %va, <vscale x 32 x i16> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i16> %v |
| } |
| |
| declare <vscale x 1 x i32> @llvm.vp.smin.nxv1i32(<vscale x 1 x i32>, <vscale x 1 x i32>, <vscale x 1 x i1>, i32) |
| |
| define <vscale x 1 x i32> @vmin_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 1 x i32> @llvm.vp.smin.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i32> %v |
| } |
| |
| define <vscale x 1 x i32> @vmin_vv_nxv1i32_unmasked(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i32> @llvm.vp.smin.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i32> %v |
| } |
| |
| define <vscale x 1 x i32> @vmin_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i32> @llvm.vp.smin.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i32> %v |
| } |
| |
| define <vscale x 1 x i32> @vmin_vx_nxv1i32_unmasked(<vscale x 1 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv1i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i32> @llvm.vp.smin.nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i32> %v |
| } |
| |
| declare <vscale x 2 x i32> @llvm.vp.smin.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, <vscale x 2 x i1>, i32) |
| |
| define <vscale x 2 x i32> @vmin_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 2 x i32> @llvm.vp.smin.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i32> %v |
| } |
| |
| define <vscale x 2 x i32> @vmin_vv_nxv2i32_unmasked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i32> @llvm.vp.smin.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i32> %v |
| } |
| |
| define <vscale x 2 x i32> @vmin_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i32> @llvm.vp.smin.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i32> %v |
| } |
| |
| define <vscale x 2 x i32> @vmin_vx_nxv2i32_unmasked(<vscale x 2 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv2i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i32> @llvm.vp.smin.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i32> %v |
| } |
| |
| declare <vscale x 4 x i32> @llvm.vp.smin.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32) |
| |
| define <vscale x 4 x i32> @vmin_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 4 x i32> @llvm.vp.smin.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i32> %v |
| } |
| |
| define <vscale x 4 x i32> @vmin_vv_nxv4i32_unmasked(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i32> @llvm.vp.smin.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i32> %v |
| } |
| |
| define <vscale x 4 x i32> @vmin_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i32> @llvm.vp.smin.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i32> %v |
| } |
| |
| define <vscale x 4 x i32> @vmin_vx_nxv4i32_unmasked(<vscale x 4 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv4i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i32> @llvm.vp.smin.nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i32> %v |
| } |
| |
| declare <vscale x 8 x i32> @llvm.vp.smin.nxv8i32(<vscale x 8 x i32>, <vscale x 8 x i32>, <vscale x 8 x i1>, i32) |
| |
| define <vscale x 8 x i32> @vmin_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 8 x i32> @llvm.vp.smin.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i32> %v |
| } |
| |
| define <vscale x 8 x i32> @vmin_vv_nxv8i32_unmasked(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i32> @llvm.vp.smin.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i32> %v |
| } |
| |
| define <vscale x 8 x i32> @vmin_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i32> @llvm.vp.smin.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i32> %v |
| } |
| |
| define <vscale x 8 x i32> @vmin_vx_nxv8i32_unmasked(<vscale x 8 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv8i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i32> @llvm.vp.smin.nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i32> %v |
| } |
| |
| declare <vscale x 16 x i32> @llvm.vp.smin.nxv16i32(<vscale x 16 x i32>, <vscale x 16 x i32>, <vscale x 16 x i1>, i32) |
| |
| define <vscale x 16 x i32> @vmin_vv_nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 16 x i32> @llvm.vp.smin.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i32> %v |
| } |
| |
| define <vscale x 16 x i32> @vmin_vv_nxv16i32_unmasked(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv16i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i32> @llvm.vp.smin.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %b, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i32> %v |
| } |
| |
| define <vscale x 16 x i32> @vmin_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i32> @llvm.vp.smin.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i32> %v |
| } |
| |
| define <vscale x 16 x i32> @vmin_vx_nxv16i32_unmasked(<vscale x 16 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv16i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer |
| %head = insertelement <vscale x 16 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer |
| %v = call <vscale x 16 x i32> @llvm.vp.smin.nxv16i32(<vscale x 16 x i32> %va, <vscale x 16 x i32> %vb, <vscale x 16 x i1> %m, i32 %evl) |
| ret <vscale x 16 x i32> %v |
| } |
| |
| ; Test that split-legalization works then the mask needs manual splitting. |
| |
| declare <vscale x 32 x i32> @llvm.vp.smin.nxv32i32(<vscale x 32 x i32>, <vscale x 32 x i32>, <vscale x 32 x i1>, i32) |
| |
| define <vscale x 32 x i32> @vmin_vx_nxv32i32(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i32: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v24, v0 |
| ; CHECK-NEXT: csrr a2, vlenb |
| ; CHECK-NEXT: srli a3, a2, 2 |
| ; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma |
| ; CHECK-NEXT: vslidedown.vx v0, v0, a3 |
| ; CHECK-NEXT: slli a2, a2, 1 |
| ; CHECK-NEXT: sub a3, a1, a2 |
| ; CHECK-NEXT: sltu a4, a1, a3 |
| ; CHECK-NEXT: addi a4, a4, -1 |
| ; CHECK-NEXT: and a3, a4, a3 |
| ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t |
| ; CHECK-NEXT: bltu a1, a2, .LBB80_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: mv a1, a2 |
| ; CHECK-NEXT: .LBB80_2: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; CHECK-NEXT: vmv1r.v v0, v24 |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i32> @llvm.vp.smin.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i32> %v |
| } |
| |
| define <vscale x 32 x i32> @vmin_vx_nxv32i32_unmasked(<vscale x 32 x i32> %va, i32 %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vx_nxv32i32_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: csrr a2, vlenb |
| ; CHECK-NEXT: slli a2, a2, 1 |
| ; CHECK-NEXT: sub a3, a1, a2 |
| ; CHECK-NEXT: sltu a4, a1, a3 |
| ; CHECK-NEXT: addi a4, a4, -1 |
| ; CHECK-NEXT: and a3, a4, a3 |
| ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v16, v16, a0 |
| ; CHECK-NEXT: bltu a1, a2, .LBB81_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: mv a1, a2 |
| ; CHECK-NEXT: .LBB81_2: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v8, v8, a0 |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer |
| %head = insertelement <vscale x 32 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 32 x i1> %head, <vscale x 32 x i1> poison, <vscale x 32 x i32> zeroinitializer |
| %v = call <vscale x 32 x i32> @llvm.vp.smin.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 %evl) |
| ret <vscale x 32 x i32> %v |
| } |
| |
| ; Test splitting when the %evl is a constant (albeit an unknown one). |
| |
| declare i32 @llvm.vscale.i32() |
| |
| ; FIXME: The upper half of the operation is doing nothing. |
| ; FIXME: The branches comparing vscale vs. vscale should be constant-foldable. |
| |
| define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx8(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) { |
| ; CHECK-LABEL: vmin_vx_nxv32i32_evl_nx8: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vmv1r.v v24, v0 |
| ; CHECK-NEXT: csrr a1, vlenb |
| ; CHECK-NEXT: srli a2, a1, 2 |
| ; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma |
| ; CHECK-NEXT: vslidedown.vx v0, v0, a2 |
| ; CHECK-NEXT: slli a2, a1, 1 |
| ; CHECK-NEXT: sub a3, a1, a2 |
| ; CHECK-NEXT: sltu a4, a1, a3 |
| ; CHECK-NEXT: addi a4, a4, -1 |
| ; CHECK-NEXT: and a3, a4, a3 |
| ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma |
| ; CHECK-NEXT: vmin.vx v16, v16, a0, v0.t |
| ; CHECK-NEXT: bltu a1, a2, .LBB82_2 |
| ; CHECK-NEXT: # %bb.1: |
| ; CHECK-NEXT: mv a1, a2 |
| ; CHECK-NEXT: .LBB82_2: |
| ; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; CHECK-NEXT: vmv1r.v v0, v24 |
| ; CHECK-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; CHECK-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer |
| %evl = call i32 @llvm.vscale.i32() |
| %evl0 = mul i32 %evl, 8 |
| %v = call <vscale x 32 x i32> @llvm.vp.smin.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 %evl0) |
| ret <vscale x 32 x i32> %v |
| } |
| |
| ; FIXME: The first vmin.vx should be able to infer that its AVL is equivalent to VLMAX. |
| ; FIXME: The upper half of the operation is doing nothing but we don't catch |
| ; that on RV64; we issue a usubsat(and (vscale x 16), 0xffffffff, vscale x 16) |
| ; (the "original" %evl is the "and", due to known-bits issues with legalizing |
| ; the i32 %evl to i64) and this isn't detected as 0. |
| ; This could be resolved in the future with more detailed KnownBits analysis |
| ; for ISD::VSCALE. |
| |
| define <vscale x 32 x i32> @vmin_vx_nxv32i32_evl_nx16(<vscale x 32 x i32> %va, i32 %b, <vscale x 32 x i1> %m) { |
| ; RV32-LABEL: vmin_vx_nxv32i32_evl_nx16: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: csrr a1, vlenb |
| ; RV32-NEXT: slli a1, a1, 1 |
| ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; RV32-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv32i32_evl_nx16: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: csrr a1, vlenb |
| ; RV64-NEXT: srli a2, a1, 2 |
| ; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma |
| ; RV64-NEXT: vslidedown.vx v24, v0, a2 |
| ; RV64-NEXT: slli a1, a1, 1 |
| ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV64-NEXT: vsetivli zero, 0, e32, m8, ta, ma |
| ; RV64-NEXT: vmv1r.v v0, v24 |
| ; RV64-NEXT: vmin.vx v16, v16, a0, v0.t |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 32 x i32> poison, i32 %b, i32 0 |
| %vb = shufflevector <vscale x 32 x i32> %elt.head, <vscale x 32 x i32> poison, <vscale x 32 x i32> zeroinitializer |
| %evl = call i32 @llvm.vscale.i32() |
| %evl0 = mul i32 %evl, 16 |
| %v = call <vscale x 32 x i32> @llvm.vp.smin.nxv32i32(<vscale x 32 x i32> %va, <vscale x 32 x i32> %vb, <vscale x 32 x i1> %m, i32 %evl0) |
| ret <vscale x 32 x i32> %v |
| } |
| |
| declare <vscale x 1 x i64> @llvm.vp.smin.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, <vscale x 1 x i1>, i32) |
| |
| define <vscale x 1 x i64> @vmin_vv_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 1 x i64> @llvm.vp.smin.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i64> %v |
| } |
| |
| define <vscale x 1 x i64> @vmin_vv_nxv1i64_unmasked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv1i64_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v9 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i64> @llvm.vp.smin.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %b, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i64> %v |
| } |
| |
| define <vscale x 1 x i64> @vmin_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv1i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma |
| ; RV32-NEXT: vlse64.v v9, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v9, v0.t |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv1i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i64> @llvm.vp.smin.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i64> %v |
| } |
| |
| define <vscale x 1 x i64> @vmin_vx_nxv1i64_unmasked(<vscale x 1 x i64> %va, i64 %b, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv1i64_unmasked: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma |
| ; RV32-NEXT: vlse64.v v9, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m1, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v9 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv1i64_unmasked: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0 |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer |
| %head = insertelement <vscale x 1 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> poison, <vscale x 1 x i32> zeroinitializer |
| %v = call <vscale x 1 x i64> @llvm.vp.smin.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %m, i32 %evl) |
| ret <vscale x 1 x i64> %v |
| } |
| |
| declare <vscale x 2 x i64> @llvm.vp.smin.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i1>, i32) |
| |
| define <vscale x 2 x i64> @vmin_vv_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 2 x i64> @llvm.vp.smin.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i64> %v |
| } |
| |
| define <vscale x 2 x i64> @vmin_vv_nxv2i64_unmasked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv2i64_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v10 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i64> @llvm.vp.smin.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %b, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i64> %v |
| } |
| |
| define <vscale x 2 x i64> @vmin_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv2i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma |
| ; RV32-NEXT: vlse64.v v10, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v10, v0.t |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv2i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i64> @llvm.vp.smin.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i64> %v |
| } |
| |
| define <vscale x 2 x i64> @vmin_vx_nxv2i64_unmasked(<vscale x 2 x i64> %va, i64 %b, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv2i64_unmasked: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma |
| ; RV32-NEXT: vlse64.v v10, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m2, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v10 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv2i64_unmasked: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0 |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer |
| %head = insertelement <vscale x 2 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer |
| %v = call <vscale x 2 x i64> @llvm.vp.smin.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %m, i32 %evl) |
| ret <vscale x 2 x i64> %v |
| } |
| |
| declare <vscale x 4 x i64> @llvm.vp.smin.nxv4i64(<vscale x 4 x i64>, <vscale x 4 x i64>, <vscale x 4 x i1>, i32) |
| |
| define <vscale x 4 x i64> @vmin_vv_nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 4 x i64> @llvm.vp.smin.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i64> %v |
| } |
| |
| define <vscale x 4 x i64> @vmin_vv_nxv4i64_unmasked(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv4i64_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v12 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i64> @llvm.vp.smin.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %b, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i64> %v |
| } |
| |
| define <vscale x 4 x i64> @vmin_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv4i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma |
| ; RV32-NEXT: vlse64.v v12, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v12, v0.t |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv4i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i64> @llvm.vp.smin.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i64> %v |
| } |
| |
| define <vscale x 4 x i64> @vmin_vx_nxv4i64_unmasked(<vscale x 4 x i64> %va, i64 %b, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv4i64_unmasked: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma |
| ; RV32-NEXT: vlse64.v v12, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m4, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v12 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv4i64_unmasked: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0 |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer |
| %head = insertelement <vscale x 4 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer |
| %v = call <vscale x 4 x i64> @llvm.vp.smin.nxv4i64(<vscale x 4 x i64> %va, <vscale x 4 x i64> %vb, <vscale x 4 x i1> %m, i32 %evl) |
| ret <vscale x 4 x i64> %v |
| } |
| |
| declare <vscale x 8 x i64> @llvm.vp.smin.nxv8i64(<vscale x 8 x i64>, <vscale x 8 x i64>, <vscale x 8 x i1>, i32) |
| |
| define <vscale x 8 x i64> @vmin_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i64: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16, v0.t |
| ; CHECK-NEXT: ret |
| %v = call <vscale x 8 x i64> @llvm.vp.smin.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i64> %v |
| } |
| |
| define <vscale x 8 x i64> @vmin_vv_nxv8i64_unmasked(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, i32 zeroext %evl) { |
| ; CHECK-LABEL: vmin_vv_nxv8i64_unmasked: |
| ; CHECK: # %bb.0: |
| ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma |
| ; CHECK-NEXT: vmin.vv v8, v8, v16 |
| ; CHECK-NEXT: ret |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i64> @llvm.vp.smin.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %b, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i64> %v |
| } |
| |
| define <vscale x 8 x i64> @vmin_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv8i64: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v16, v0.t |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv8i64: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0, v0.t |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i64> @llvm.vp.smin.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i64> %v |
| } |
| |
| define <vscale x 8 x i64> @vmin_vx_nxv8i64_unmasked(<vscale x 8 x i64> %va, i64 %b, i32 zeroext %evl) { |
| ; RV32-LABEL: vmin_vx_nxv8i64_unmasked: |
| ; RV32: # %bb.0: |
| ; RV32-NEXT: addi sp, sp, -16 |
| ; RV32-NEXT: .cfi_def_cfa_offset 16 |
| ; RV32-NEXT: sw a1, 12(sp) |
| ; RV32-NEXT: sw a0, 8(sp) |
| ; RV32-NEXT: addi a0, sp, 8 |
| ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma |
| ; RV32-NEXT: vlse64.v v16, (a0), zero |
| ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma |
| ; RV32-NEXT: vmin.vv v8, v8, v16 |
| ; RV32-NEXT: addi sp, sp, 16 |
| ; RV32-NEXT: ret |
| ; |
| ; RV64-LABEL: vmin_vx_nxv8i64_unmasked: |
| ; RV64: # %bb.0: |
| ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma |
| ; RV64-NEXT: vmin.vx v8, v8, a0 |
| ; RV64-NEXT: ret |
| %elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 |
| %vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer |
| %head = insertelement <vscale x 8 x i1> poison, i1 true, i32 0 |
| %m = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> poison, <vscale x 8 x i32> zeroinitializer |
| %v = call <vscale x 8 x i64> @llvm.vp.smin.nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb, <vscale x 8 x i1> %m, i32 %evl) |
| ret <vscale x 8 x i64> %v |
| } |