llvm/test/CodeGen/RISCV/pr68855.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define i16 @narrow_load(ptr %p1, ptr %p2) {
; CHECK-LABEL: narrow_load:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lhu a2, 0(a0)
; CHECK-NEXT:    lui a3, 2
; CHECK-NEXT:    addiw a3, a3, -1
; CHECK-NEXT:    xor a2, a2, a3
; CHECK-NEXT:    lui a4, 16
; CHECK-NEXT:    addi a4, a4, -1
; CHECK-NEXT:    xor a4, a3, a4
; CHECK-NEXT:    or a2, a2, a4
; CHECK-NEXT:    sw a2, 0(a1)
; CHECK-NEXT:    lhu a0, 0(a0)
; CHECK-NEXT:    and a0, a0, a3
; CHECK-NEXT:    ret
entry:
  %bf.load = load i16, ptr %p1, align 2
  %bf.clear = and i16 %bf.load, 8191
  %not = xor i16 %bf.clear, -1
  %conv1 = zext i16 %not to i32
  store i32 %conv1, ptr %p2, align 4
  %bf.load2 = load i16, ptr %p1, align 2
  %bf.clear3 = and i16 %bf.load2, 8191
  ret i16 %bf.clear3
}