| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ |
| ; RUN: -mcpu=pwr8 < %s | FileCheck %s |
| ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr8 \ |
| ; RUN: < %s -vec-extabi | FileCheck %s |
| |
| %class.PB2 = type { [1 x i32], ptr } |
| %class.PB1 = type { [1 x i32], i64, i64, i32 } |
| |
| ; Function Attrs: norecurse nounwind readonly |
| define zeroext i1 @test1(ptr %s_a, ptr %s_b) local_unnamed_addr #0 { |
| ; CHECK-LABEL: test1: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lwz 3, 0(3) |
| ; CHECK-NEXT: lwz 4, 0(4) |
| ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 |
| ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 |
| ; CHECK-NEXT: sub 3, 3, 4 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = load i32, ptr %s_a, align 8, !tbaa !1 |
| %and.i = and i32 %0, 8 |
| %1 = load i32, ptr %s_b, align 8, !tbaa !1 |
| %and.i4 = and i32 %1, 8 |
| %cmp.i5 = icmp ult i32 %and.i, %and.i4 |
| ret i1 %cmp.i5 |
| } |
| |
| ; Function Attrs: norecurse nounwind readonly |
| define zeroext i1 @test2(ptr %s_a, ptr %s_b) local_unnamed_addr #0 { |
| ; CHECK-LABEL: test2: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lwz 3, 0(3) |
| ; CHECK-NEXT: lwz 4, 0(4) |
| ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 |
| ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 |
| ; CHECK-NEXT: sub 3, 4, 3 |
| ; CHECK-NEXT: not 3, 3 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = load i32, ptr %s_a, align 8, !tbaa !1 |
| %and.i = and i32 %0, 8 |
| %1 = load i32, ptr %s_b, align 8, !tbaa !1 |
| %and.i4 = and i32 %1, 8 |
| %cmp.i5 = icmp ule i32 %and.i, %and.i4 |
| ret i1 %cmp.i5 |
| } |
| |
| ; Function Attrs: norecurse nounwind readonly |
| define zeroext i1 @test3(ptr %s_a, ptr %s_b) local_unnamed_addr #0 { |
| ; CHECK-LABEL: test3: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lwz 3, 0(3) |
| ; CHECK-NEXT: lwz 4, 0(4) |
| ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 |
| ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 |
| ; CHECK-NEXT: sub 3, 4, 3 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = load i32, ptr %s_a, align 8, !tbaa !1 |
| %and.i = and i32 %0, 8 |
| %1 = load i32, ptr %s_b, align 8, !tbaa !1 |
| %and.i4 = and i32 %1, 8 |
| %cmp.i5 = icmp ugt i32 %and.i, %and.i4 |
| ret i1 %cmp.i5 |
| } |
| |
| ; Function Attrs: norecurse nounwind readonly |
| define zeroext i1 @test4(ptr %s_a, ptr %s_b) local_unnamed_addr #0 { |
| ; CHECK-LABEL: test4: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lwz 3, 0(3) |
| ; CHECK-NEXT: lwz 4, 0(4) |
| ; CHECK-NEXT: rlwinm 3, 3, 0, 28, 28 |
| ; CHECK-NEXT: rlwinm 4, 4, 0, 28, 28 |
| ; CHECK-NEXT: sub 3, 3, 4 |
| ; CHECK-NEXT: not 3, 3 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = load i32, ptr %s_a, align 8, !tbaa !1 |
| %and.i = and i32 %0, 8 |
| %1 = load i32, ptr %s_b, align 8, !tbaa !1 |
| %and.i4 = and i32 %1, 8 |
| %cmp.i5 = icmp uge i32 %and.i, %and.i4 |
| ret i1 %cmp.i5 |
| } |
| |
| define zeroext i1 @test5(i64 %a) { |
| ; CHECK-LABEL: test5: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: li 4, -1 |
| ; CHECK-NEXT: addis 3, 3, -32768 |
| ; CHECK-NEXT: rldic 4, 4, 32, 0 |
| ; CHECK-NEXT: subc 4, 3, 4 |
| ; CHECK-NEXT: subfe 3, 3, 3 |
| ; CHECK-NEXT: neg 3, 3 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i64 %a, -2147483648 |
| %cmp = icmp ult i64 %0, -4294967296 |
| ret i1 %cmp |
| } |
| |
| define zeroext i1 @test6(i64 %a) { |
| ; CHECK-LABEL: test6: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: addi 3, 3, -32768 |
| ; CHECK-NEXT: lis 4, -1 |
| ; CHECK-NEXT: subc 4, 3, 4 |
| ; CHECK-NEXT: subfe 3, 3, 3 |
| ; CHECK-NEXT: neg 3, 3 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i64 %a, -32768 |
| %cmp = icmp ult i64 %0, -65536 |
| ret i1 %cmp |
| } |
| |
| define zeroext i1 @test7(i64 %a) { |
| ; CHECK-LABEL: test7: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: addi 3, 3, -128 |
| ; CHECK-NEXT: li 4, -256 |
| ; CHECK-NEXT: subc 4, 3, 4 |
| ; CHECK-NEXT: subfe 3, 3, 3 |
| ; CHECK-NEXT: neg 3, 3 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i64 %a, -128 |
| %cmp = icmp ult i64 %0, -256 |
| ret i1 %cmp |
| } |
| |
| define zeroext i1 @test8(i32 %a) { |
| ; CHECK-LABEL: test8: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: addi 3, 3, -32768 |
| ; CHECK-NEXT: lis 4, -1 |
| ; CHECK-NEXT: rlwinm 3, 3, 16, 16, 31 |
| ; CHECK-NEXT: ori 4, 4, 1 |
| ; CHECK-NEXT: add 3, 3, 4 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i32 %a, -32768 |
| %cmp = icmp ult i32 %0, -65536 |
| ret i1 %cmp |
| } |
| |
| define zeroext i1 @test9(i32 %a) { |
| ; CHECK-LABEL: test9: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: lis 4, -256 |
| ; CHECK-NEXT: addi 3, 3, -128 |
| ; CHECK-NEXT: ori 4, 4, 1 |
| ; CHECK-NEXT: clrldi 3, 3, 32 |
| ; CHECK-NEXT: rldic 4, 4, 8, 0 |
| ; CHECK-NEXT: add 3, 3, 4 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i32 %a, -128 |
| %cmp = icmp ult i32 %0, -256 |
| ret i1 %cmp |
| } |
| |
| define zeroext i1 @test10(i16 %a) { |
| ; CHECK-LABEL: test10: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: addi 3, 3, -128 |
| ; CHECK-NEXT: lis 4, -1 |
| ; CHECK-NEXT: clrlwi 3, 3, 16 |
| ; CHECK-NEXT: ori 4, 4, 256 |
| ; CHECK-NEXT: add 3, 3, 4 |
| ; CHECK-NEXT: rldicl 3, 3, 1, 63 |
| ; CHECK-NEXT: blr |
| entry: |
| %0 = add i16 %a, -128 |
| %cmp = icmp ult i16 %0, -256 |
| ret i1 %cmp |
| } |
| |
| !1 = !{!2, !2, i64 0} |
| !2 = !{!"int", !3, i64 0} |
| !3 = !{!"omnipotent char", !4, i64 0} |
| !4 = !{!"Simple C++ TBAA"} |