llvm/test/CodeGen/PowerPC/pr25080.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=LE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mcpu=pwr8 < %s | FileCheck %s --check-prefix=BE

define <8 x i16> @pr25080(<8 x i32> %a) {
; LE-LABEL: pr25080:
; LE:       # %bb.0: # %entry
; LE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; LE-NEXT:    xxlxor 34, 34, 34
; LE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; LE-NEXT:    lxvd2x 0, 0, 3
; LE-NEXT:    xxland 35, 35, 0
; LE-NEXT:    vcmpequw 2, 3, 2
; LE-NEXT:    mfvsrwz 3, 34
; LE-NEXT:    xxsldwi 0, 34, 34, 1
; LE-NEXT:    xxswapd 1, 34
; LE-NEXT:    xxsldwi 2, 34, 34, 3
; LE-NEXT:    mffprwz 5, 0
; LE-NEXT:    mffprwz 6, 1
; LE-NEXT:    mffprwz 4, 2
; LE-NEXT:    mtvsrd 34, 3
; LE-NEXT:    li 3, -1
; LE-NEXT:    mtvsrd 35, 6
; LE-NEXT:    mtvsrd 36, 5
; LE-NEXT:    vmrghh 3, 4, 3
; LE-NEXT:    mtvsrd 36, 4
; LE-NEXT:    vmrghh 2, 4, 2
; LE-NEXT:    mtvsrd 36, 3
; LE-NEXT:    xxmrglw 0, 34, 35
; LE-NEXT:    vsplth 4, 4, 3
; LE-NEXT:    xxspltw 1, 36, 3
; LE-NEXT:    xxmrgld 34, 0, 1
; LE-NEXT:    blr
;
; BE-LABEL: pr25080:
; BE:       # %bb.0: # %entry
; BE-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; BE-NEXT:    xxlxor 34, 34, 34
; BE-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; BE-NEXT:    lxvw4x 0, 0, 3
; BE-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
; BE-NEXT:    addi 3, 3, .LCPI0_1@toc@l
; BE-NEXT:    xxland 35, 35, 0
; BE-NEXT:    vcmpequw 2, 3, 2
; BE-NEXT:    mfvsrwz 4, 34
; BE-NEXT:    mtvsrwz 35, 4
; BE-NEXT:    xxsldwi 0, 34, 34, 1
; BE-NEXT:    xxswapd 1, 34
; BE-NEXT:    mffprwz 5, 0
; BE-NEXT:    mffprwz 6, 1
; BE-NEXT:    xxsldwi 2, 34, 34, 3
; BE-NEXT:    lxvw4x 34, 0, 3
; BE-NEXT:    mffprwz 3, 2
; BE-NEXT:    mtvsrwz 36, 6
; BE-NEXT:    mtvsrwz 37, 5
; BE-NEXT:    vperm 4, 5, 4, 2
; BE-NEXT:    mtvsrwz 37, 3
; BE-NEXT:    li 3, -1
; BE-NEXT:    vperm 2, 5, 3, 2
; BE-NEXT:    mtvsrwz 35, 3
; BE-NEXT:    xxmrghw 0, 34, 36
; BE-NEXT:    vsplth 3, 3, 3
; BE-NEXT:    xxspltw 1, 35, 0
; BE-NEXT:    xxmrghd 34, 1, 0
; BE-NEXT:    blr
entry:
  %0 = trunc <8 x i32> %a to <8 x i23>
  %1 = icmp eq <8 x i23> %0, zeroinitializer
  %2 = or <8 x i1> %1, <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>
  %3 = sext <8 x i1> %2 to <8 x i16>
  ret <8 x i16> %3
}