llvm/test/CodeGen/AMDGPU/llvm.amdgcn.class.f16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI-SDAG %s
; RUN: llc -global-isel=1 -new-reg-bank-select -amdgpu-scalarize-global-loads=false -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI-GISEL %s

declare half @llvm.fabs.f16(half %a)
declare i1 @llvm.amdgcn.class.f16(half %a, i32 %b)

define amdgpu_kernel void @class_f16(
; VI-SDAG-LABEL: class_f16:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; VI-SDAG-NEXT:    s_load_dwordx2 s[8:9], s[8:9], 0x10
; VI-SDAG-NEXT:    s_mov_b32 s7, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s6, -1
; VI-SDAG-NEXT:    s_mov_b32 s10, s6
; VI-SDAG-NEXT:    s_mov_b32 s11, s7
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    s_mov_b32 s12, s2
; VI-SDAG-NEXT:    s_mov_b32 s13, s3
; VI-SDAG-NEXT:    s_mov_b32 s14, s6
; VI-SDAG-NEXT:    s_mov_b32 s15, s7
; VI-SDAG-NEXT:    buffer_load_dword v0, off, s[8:11], 0
; VI-SDAG-NEXT:    buffer_load_ushort v1, off, s[12:15], 0
; VI-SDAG-NEXT:    s_mov_b32 s4, s0
; VI-SDAG-NEXT:    s_mov_b32 s5, s1
; VI-SDAG-NEXT:    s_waitcnt vmcnt(0)
; VI-SDAG-NEXT:    v_cmp_class_f16_e32 vcc, v1, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[4:7], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s6, -1
; VI-GISEL-NEXT:    s_mov_b32 s7, 0x1100f000
; VI-GISEL-NEXT:    s_load_dwordx2 s[8:9], s[8:9], 0x10
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    s_mov_b64 s[4:5], s[2:3]
; VI-GISEL-NEXT:    buffer_load_ushort v0, off, s[4:7], 0
; VI-GISEL-NEXT:    s_load_dword s2, s[8:9], 0x0
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_mov_b32_e32 v1, s2
; VI-GISEL-NEXT:    s_waitcnt vmcnt(0)
; VI-GISEL-NEXT:    v_readfirstlane_b32 s2, v0
; VI-GISEL-NEXT:    v_cmp_class_f16_e32 vcc, s2, v1
; VI-GISEL-NEXT:    s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT:    s_cselect_b32 s2, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; VI-GISEL-NEXT:    s_mov_b64 s[2:3], s[6:7]
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
    ptr addrspace(1) %r,
    ptr addrspace(1) %a,
    ptr addrspace(1) %b) {
entry:
  %a.val = load half, ptr addrspace(1) %a
  %b.val = load i32, ptr addrspace(1) %b
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 %b.val)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_fabs(
; VI-SDAG-LABEL: class_f16_fabs:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x4c
; VI-SDAG-NEXT:    s_load_dword s5, s[8:9], 0x28
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT:    v_cmp_class_f16_e64 s[4:5], |s5|, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_fabs:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x4c
; VI-GISEL-NEXT:    s_load_dword s4, s[8:9], 0x28
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    v_cmp_class_f16_e64 s[4:5], |s4|, v0
; VI-GISEL-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  [8 x i32],
  half %a.val,
  [8 x i32],
  i32 %b.val) {
entry:
  %a.val.fabs = call half @llvm.fabs.f16(half %a.val)
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fabs, i32 %b.val)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_fneg(
; VI-SDAG-LABEL: class_f16_fneg:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x4c
; VI-SDAG-NEXT:    s_load_dword s5, s[8:9], 0x28
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT:    v_cmp_class_f16_e64 s[4:5], -s5, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_fneg:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x28
; VI-GISEL-NEXT:    s_load_dword s4, s[8:9], 0x4c
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_max_f16_e64 v0, -s3, -s3
; VI-GISEL-NEXT:    v_cmp_class_f16_e64 s[4:5], v0, s4
; VI-GISEL-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  [8 x i32],
  half %a.val,
  [8 x i32],
  i32 %b.val) {
entry:
  %a.val.fneg = fsub half -0.0, %a.val
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fneg, i32 %b.val)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_fabs_fneg(
; VI-SDAG-LABEL: class_f16_fabs_fneg:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x4c
; VI-SDAG-NEXT:    s_load_dword s5, s[8:9], 0x28
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_mov_b32_e32 v0, s4
; VI-SDAG-NEXT:    v_cmp_class_f16_e64 s[4:5], -|s5|, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_fabs_fneg:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x28
; VI-GISEL-NEXT:    s_load_dword s4, s[8:9], 0x4c
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_max_f16_e64 v0, -|s3|, -|s3|
; VI-GISEL-NEXT:    v_cmp_class_f16_e64 s[4:5], v0, s4
; VI-GISEL-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  [8 x i32],
  half %a.val,
  [8 x i32],
  i32 %b.val) {
entry:
  %a.val.fabs = call half @llvm.fabs.f16(half %a.val)
  %a.val.fabs.fneg = fsub half -0.0, %a.val.fabs
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val.fabs.fneg, i32 %b.val)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_1(
; VI-SDAG-LABEL: class_f16_1:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x8
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_cmp_class_f16_e64 s[4:5], s4, 1
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_1:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x8
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_cmp_class_f16_e64 s[4:5], s3, 1
; VI-GISEL-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  half %a.val) {
entry:
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 1)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_64(
; VI-SDAG-LABEL: class_f16_64:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x8
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_cmp_class_f16_e64 s[4:5], s4, 64
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, s[4:5]
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_64:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x8
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_cmp_class_f16_e64 s[4:5], s3, 64
; VI-GISEL-NEXT:    s_cmp_lg_u64 s[4:5], 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  half %a.val) {
entry:
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 64)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_full_mask(
; VI-SDAG-LABEL: class_f16_full_mask:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x8
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x3ff
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_cmp_class_f16_e32 vcc, s4, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_full_mask:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x8
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x3ff
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_cmp_class_f16_e32 vcc, s3, v0
; VI-GISEL-NEXT:    s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  half %a.val) {
entry:
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 1023)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}

define amdgpu_kernel void @class_f16_nine_bit_mask(
; VI-SDAG-LABEL: class_f16_nine_bit_mask:
; VI-SDAG:       ; %bb.0: ; %entry
; VI-SDAG-NEXT:    s_load_dword s4, s[8:9], 0x8
; VI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-SDAG-NEXT:    v_mov_b32_e32 v0, 0x1ff
; VI-SDAG-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-SDAG-NEXT:    s_mov_b32 s2, -1
; VI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; VI-SDAG-NEXT:    v_cmp_class_f16_e32 vcc, s4, v0
; VI-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, -1, vcc
; VI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-SDAG-NEXT:    s_endpgm
;
; VI-GISEL-LABEL: class_f16_nine_bit_mask:
; VI-GISEL:       ; %bb.0: ; %entry
; VI-GISEL-NEXT:    s_load_dword s3, s[8:9], 0x8
; VI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, 0x1ff
; VI-GISEL-NEXT:    s_mov_b32 s2, -1
; VI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; VI-GISEL-NEXT:    v_cmp_class_f16_e32 vcc, s3, v0
; VI-GISEL-NEXT:    s_cmp_lg_u64 vcc, 0
; VI-GISEL-NEXT:    s_cselect_b32 s3, -1, 0
; VI-GISEL-NEXT:    v_mov_b32_e32 v0, s3
; VI-GISEL-NEXT:    s_mov_b32 s3, 0x1100f000
; VI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; VI-GISEL-NEXT:    s_endpgm
  ptr addrspace(1) %r,
  half %a.val) {
entry:
  %r.val = call i1 @llvm.amdgcn.class.f16(half %a.val, i32 511)
  %r.val.sext = sext i1 %r.val to i32
  store i32 %r.val.sext, ptr addrspace(1) %r
  ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}