llvm/test/CodeGen/AMDGPU/amdgcn-sin-cos-f16-f32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_setreg_imm32_b32" --filter-out "shader" --version 6
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GCN,FAKE16 %s
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GCN,REAL16 %s

define amdgpu_ps float @v_sin_f32(float %src) #1 {
; GCN-LABEL: v_sin_f32:
; GCN:  ; %bb.0:
; GCN:    v_sin_f32_e32 v0, v0
  %sin = call float @llvm.amdgcn.sin.f32(float %src) #0
  ret float %sin
}

define amdgpu_ps float @s_sin_f32(float inreg %src) #1 {
; GCN-LABEL: s_sin_f32:
; GCN:  ; %bb.0:
; GCN:    v_sin_f32_e32 v0, s0
  %sin = call float @llvm.amdgcn.sin.f32(float %src) #0
  ret float %sin
}

define amdgpu_ps half @v_sin_f16(half %src) #1 {
; FAKE16-LABEL: v_sin_f16:
; FAKE16:  ; %bb.0:
; FAKE16:    v_sin_f16_e32 v0, v0
;
; REAL16-LABEL: v_sin_f16:
; REAL16:  ; %bb.0:
; REAL16:    v_sin_f16_e32 v0.l, v0.l
  %sin = call half @llvm.amdgcn.sin.f16(half %src) #0
  ret half %sin
}

define amdgpu_ps half @s_sin_f16(half inreg %src) #1 {
; FAKE16-LABEL: s_sin_f16:
; FAKE16:  ; %bb.0:
; FAKE16:    v_sin_f16_e32 v0, s0
;
; REAL16-LABEL: s_sin_f16:
; REAL16:  ; %bb.0:
; REAL16:    v_sin_f16_e32 v0.l, s0
  %sin = call half @llvm.amdgcn.sin.f16(half %src) #0
  ret half %sin
}

define amdgpu_ps float @v_cos_f32(float %src) #1 {
; GCN-LABEL: v_cos_f32:
; GCN:  ; %bb.0:
; GCN:    v_cos_f32_e32 v0, v0
  %cos = call float @llvm.amdgcn.cos.f32(float %src) #0
  ret float %cos
}

define amdgpu_ps float @s_cos_f32(float inreg %src) #1 {
; GCN-LABEL: s_cos_f32:
; GCN:  ; %bb.0:
; GCN:    v_cos_f32_e32 v0, s0
  %cos = call float @llvm.amdgcn.cos.f32(float %src) #0
  ret float %cos
}

define amdgpu_ps half @v_cos_f16(half %src) #1 {
; FAKE16-LABEL: v_cos_f16:
; FAKE16:  ; %bb.0:
; FAKE16:    v_cos_f16_e32 v0, v0
;
; REAL16-LABEL: v_cos_f16:
; REAL16:  ; %bb.0:
; REAL16:    v_cos_f16_e32 v0.l, v0.l
  %cos = call half @llvm.amdgcn.cos.f16(half %src) #0
  ret half %cos
}

define amdgpu_ps half @s_cos_f16(half inreg %src) #1 {
; FAKE16-LABEL: s_cos_f16:
; FAKE16:  ; %bb.0:
; FAKE16:    v_cos_f16_e32 v0, s0
;
; REAL16-LABEL: s_cos_f16:
; REAL16:  ; %bb.0:
; REAL16:    v_cos_f16_e32 v0.l, s0
  %cos = call half @llvm.amdgcn.cos.f16(half %src) #0
  ret half %cos
}


declare float @llvm.amdgcn.sin.f32(float) #0
declare half @llvm.amdgcn.sin.f16(half) #0

declare float @llvm.amdgcn.cos.f32(float) #0
declare half @llvm.amdgcn.cos.f16(half) #0

attributes #0 = { nounwind readnone }
attributes #1 = { nounwind }