llvm/test/CodeGen/ARM/cls.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv5 %s -o - | FileCheck %s --check-prefixes=CHECKV5
; RUN: llc -mtriple=thumbv8.1-m.main %s -o - | FileCheck %s --check-prefix=CHECKV8

define i32 @cls(i32 %t) {
; CHECKV5-LABEL: cls:
; CHECKV5:       @ %bb.0:
; CHECKV5-NEXT:    eor r0, r0, r0, asr #31
; CHECKV5-NEXT:    mov r1, #1
; CHECKV5-NEXT:    orr r0, r1, r0, lsl #1
; CHECKV5-NEXT:    clz r0, r0
; CHECKV5-NEXT:    bx lr
;
; CHECKV8-LABEL: cls:
; CHECKV8:       @ %bb.0:
; CHECKV8-NEXT:    push {r7, lr}
; CHECKV8-NEXT:    asrs r1, r0, #31
; CHECKV8-NEXT:    eors r1, r0
; CHECKV8-NEXT:    lsls r0, r1, #1
; CHECKV8-NEXT:    adds r0, r0, #1
; CHECKV8-NEXT:    bl __clzsi2
; CHECKV8-NEXT:    pop {r7}
; CHECKV8-NEXT:    pop {r1}
; CHECKV8-NEXT:    bx r1
  %cls.i = call i32 @llvm.arm.cls(i32 %t)
  ret i32 %cls.i
}

define i32 @cls64(i64 %t) {
; CHECKV5-LABEL: cls64:
; CHECKV5:       @ %bb.0:
; CHECKV5-NEXT:    cmp r1, #0
; CHECKV5-NEXT:    mvnmi r0, r0
; CHECKV5-NEXT:    clz r2, r0
; CHECKV5-NEXT:    eor r0, r1, r1, asr #31
; CHECKV5-NEXT:    mov r1, #1
; CHECKV5-NEXT:    orr r0, r1, r0, lsl #1
; CHECKV5-NEXT:    clz r0, r0
; CHECKV5-NEXT:    cmp r0, #31
; CHECKV5-NEXT:    addeq r0, r2, #31
; CHECKV5-NEXT:    bx lr
;
; CHECKV8-LABEL: cls64:
; CHECKV8:       @ %bb.0:
; CHECKV8-NEXT:    push {r4, lr}
; CHECKV8-NEXT:    movs r4, r0
; CHECKV8-NEXT:    cmp r1, #0
; CHECKV8-NEXT:    bpl .LBB1_2
; CHECKV8-NEXT:  @ %bb.1:
; CHECKV8-NEXT:    mvns r4, r4
; CHECKV8-NEXT:  .LBB1_2:
; CHECKV8-NEXT:    asrs r0, r1, #31
; CHECKV8-NEXT:    eors r0, r1
; CHECKV8-NEXT:    lsls r0, r0, #1
; CHECKV8-NEXT:    adds r0, r0, #1
; CHECKV8-NEXT:    bl __clzsi2
; CHECKV8-NEXT:    cmp r0, #31
; CHECKV8-NEXT:    bne .LBB1_4
; CHECKV8-NEXT:  @ %bb.3:
; CHECKV8-NEXT:    lsrs r0, r4, #1
; CHECKV8-NEXT:    orrs r0, r4
; CHECKV8-NEXT:    lsrs r1, r0, #2
; CHECKV8-NEXT:    orrs r1, r0
; CHECKV8-NEXT:    lsrs r0, r1, #4
; CHECKV8-NEXT:    orrs r0, r1
; CHECKV8-NEXT:    lsrs r1, r0, #8
; CHECKV8-NEXT:    orrs r1, r0
; CHECKV8-NEXT:    lsrs r0, r1, #16
; CHECKV8-NEXT:    orrs r0, r1
; CHECKV8-NEXT:    mvns r0, r0
; CHECKV8-NEXT:    lsrs r1, r0, #1
; CHECKV8-NEXT:    ldr r2, .LCPI1_0
; CHECKV8-NEXT:    ands r2, r1
; CHECKV8-NEXT:    subs r0, r0, r2
; CHECKV8-NEXT:    ldr r1, .LCPI1_1
; CHECKV8-NEXT:    lsrs r2, r0, #2
; CHECKV8-NEXT:    ands r0, r1
; CHECKV8-NEXT:    ands r2, r1
; CHECKV8-NEXT:    adds r0, r0, r2
; CHECKV8-NEXT:    lsrs r1, r0, #4
; CHECKV8-NEXT:    adds r0, r0, r1
; CHECKV8-NEXT:    ldr r1, .LCPI1_2
; CHECKV8-NEXT:    ands r1, r0
; CHECKV8-NEXT:    ldr r0, .LCPI1_3
; CHECKV8-NEXT:    muls r0, r1, r0
; CHECKV8-NEXT:    lsrs r0, r0, #24
; CHECKV8-NEXT:    adds r0, #31
; CHECKV8-NEXT:  .LBB1_4:
; CHECKV8-NEXT:    pop {r4}
; CHECKV8-NEXT:    pop {r1}
; CHECKV8-NEXT:    bx r1
; CHECKV8-NEXT:    .p2align 2
; CHECKV8-NEXT:  @ %bb.5:
; CHECKV8-NEXT:  .LCPI1_0:
; CHECKV8-NEXT:    .long 1431655765 @ 0x55555555
; CHECKV8-NEXT:  .LCPI1_1:
; CHECKV8-NEXT:    .long 858993459 @ 0x33333333
; CHECKV8-NEXT:  .LCPI1_2:
; CHECKV8-NEXT:    .long 252645135 @ 0xf0f0f0f
; CHECKV8-NEXT:  .LCPI1_3:
; CHECKV8-NEXT:    .long 16843009 @ 0x1010101
  %cls.i = call i32 @llvm.arm.cls64(i64 %t)
  ret i32 %cls.i
}