llvm/test/CodeGen/AMDGPU/amd.endpgm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GFX9,GFX9-SDAG
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GFX9,GFX9-GISEL
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s --check-prefixes=GFX10,GFX10-SDAG
; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s --check-prefixes=GFX10,GFX10-GISEL
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11,GFX11-SDAG
; RUN: llc -global-isel=1  -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s --check-prefixes=GFX11,GFX11-GISEL

define amdgpu_kernel void @test0() {
; GFX9-LABEL: test0:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test0:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test0:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.endpgm()
  unreachable
}

define void @test1() {
; GFX9-LABEL: test1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    s_endpgm
;
; GFX10-LABEL: test1:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_endpgm
;
; GFX11-LABEL: test1:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    s_endpgm
  tail call void @llvm.amdgcn.endpgm()
  unreachable
}

define amdgpu_kernel void @test2(ptr %p, i32 %x) {
; GFX9-SDAG-LABEL: test2:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_load_dword s0, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_cmp_lt_i32 s0, 1
; GFX9-SDAG-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX9-SDAG-NEXT:  ; %bb.1: ; %else
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s2
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT:    flat_store_dword v[0:1], v2
; GFX9-SDAG-NEXT:    s_endpgm
; GFX9-SDAG-NEXT:  .LBB2_2: ; %then
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: test2:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_load_dword s0, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_cmp_le_i32 s0, 0
; GFX9-GISEL-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX9-GISEL-NEXT:  ; %bb.1: ; %else
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT:    flat_store_dword v[0:1], v2
; GFX9-GISEL-NEXT:    s_endpgm
; GFX9-GISEL-NEXT:  .LBB2_2: ; %then
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX10-SDAG-LABEL: test2:
; GFX10-SDAG:       ; %bb.0:
; GFX10-SDAG-NEXT:    s_load_dword s0, s[4:5], 0x2c
; GFX10-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-SDAG-NEXT:    s_cmp_lt_i32 s0, 1
; GFX10-SDAG-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX10-SDAG-NEXT:  ; %bb.1: ; %else
; GFX10-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX10-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-SDAG-NEXT:    v_mov_b32_e32 v0, s2
; GFX10-SDAG-NEXT:    v_mov_b32_e32 v1, s3
; GFX10-SDAG-NEXT:    flat_store_dword v[0:1], v2
; GFX10-SDAG-NEXT:    s_endpgm
; GFX10-SDAG-NEXT:  .LBB2_2: ; %then
; GFX10-SDAG-NEXT:    s_endpgm
;
; GFX10-GISEL-LABEL: test2:
; GFX10-GISEL:       ; %bb.0:
; GFX10-GISEL-NEXT:    s_load_dword s0, s[4:5], 0x2c
; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT:    s_cmp_le_i32 s0, 0
; GFX10-GISEL-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX10-GISEL-NEXT:  ; %bb.1: ; %else
; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX10-GISEL-NEXT:    v_mov_b32_e32 v2, s0
; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, s3
; GFX10-GISEL-NEXT:    flat_store_dword v[0:1], v2
; GFX10-GISEL-NEXT:    s_endpgm
; GFX10-GISEL-NEXT:  .LBB2_2: ; %then
; GFX10-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: test2:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_load_b32 s0, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    s_cmp_lt_i32 s0, 1
; GFX11-SDAG-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX11-SDAG-NEXT:  ; %bb.1: ; %else
; GFX11-SDAG-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v2, s0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-SDAG-NEXT:    flat_store_b32 v[0:1], v2
; GFX11-SDAG-NEXT:    s_endpgm
; GFX11-SDAG-NEXT:  .LBB2_2: ; %then
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: test2:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_load_b32 s0, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    s_cmp_le_i32 s0, 0
; GFX11-GISEL-NEXT:    s_cbranch_scc0 .LBB2_2
; GFX11-GISEL-NEXT:  ; %bb.1: ; %else
; GFX11-GISEL-NEXT:    s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v2, s0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-GISEL-NEXT:    flat_store_b32 v[0:1], v2
; GFX11-GISEL-NEXT:    s_endpgm
; GFX11-GISEL-NEXT:  .LBB2_2: ; %then
; GFX11-GISEL-NEXT:    s_endpgm
  %cond = icmp sgt i32 %x, 0
  br i1 %cond, label %then, label %else

then:
  tail call void @llvm.amdgcn.endpgm()
  unreachable

else:
  store i32 %x, ptr %p
  ret void
}

declare void @llvm.amdgcn.endpgm()