llvm/test/CodeGen/X86/pr192034.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512fp16 | FileCheck %s

define <8 x half> @maskload_v8f16_byval(<8 x half> %src, i8 %k, ptr %mem_addr) {
; CHECK-LABEL: maskload_v8f16_byval:
; CHECK:       # %bb.0:
; CHECK-NEXT:    kmovd %edi, %k1
; CHECK-NEXT:    vmovsh {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT:    retq
  %bit = and i8 %k, 1
  %zext = shufflevector <8 x half> %src, <8 x half> <half 0xH0000, half poison, half poison, half poison, half poison, half poison, half poison, half poison>, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
  %msk = bitcast i8 %bit to <8 x i1>
  %res = tail call <8 x half> @llvm.masked.load.v8f16.p0(ptr %mem_addr, <8 x i1> %msk, <8 x half> %zext)
  ret <8 x half> %res
}

define <8 x half> @maskload_v8f16_byref(ptr %p, i8 %k, ptr %mem_addr) {
; CHECK-LABEL: maskload_v8f16_byref:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vmovsh {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT:    kmovd %esi, %k1
; CHECK-NEXT:    vmovsh {{.*#+}} xmm0 {%k1} = mem[0],zero,zero,zero,zero,zero,zero,zero
; CHECK-NEXT:    retq
  %src = load <8 x half>, ptr %p, align 16
  %bit = and i8 %k, 1
  %zext = shufflevector <8 x half> %src, <8 x half> <half 0xH0000, half poison, half poison, half poison, half poison, half poison, half poison, half poison>, <8 x i32> <i32 0, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
  %msk = bitcast i8 %bit to <8 x i1>
  %res = tail call <8 x half> @llvm.masked.load.v8f16.p0(ptr %mem_addr, <8 x i1> %msk, <8 x half> %zext)
  ret <8 x half> %res
}