llvm/test/CodeGen/X86/pr173924.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s

define i256 @PR173924(<8 x i256> %a0) {
; CHECK-LABEL: PR173924:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movq %rdi, %rax
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rdi
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rdx
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rcx
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %r8
; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %r10
; CHECK-NEXT:    vmovd {{.*#+}} xmm0 = [1,0,0,0]
; CHECK-NEXT:    vpand {{[0-9]+}}(%rsp), %ymm0, %ymm0
; CHECK-NEXT:    vmovq %xmm0, %r11
; CHECK-NEXT:    andl $1, %r10d
; CHECK-NEXT:    andl $1, %esi
; CHECK-NEXT:    addq %r10, %rsi
; CHECK-NEXT:    andl $1, %r8d
; CHECK-NEXT:    andl $1, %ecx
; CHECK-NEXT:    addq %r8, %rcx
; CHECK-NEXT:    addq %rsi, %rcx
; CHECK-NEXT:    andl $1, %edx
; CHECK-NEXT:    addq %r11, %rdx
; CHECK-NEXT:    andl $1, %edi
; CHECK-NEXT:    andl $1, %r9d
; CHECK-NEXT:    addq %rdi, %r9
; CHECK-NEXT:    addq %rdx, %r9
; CHECK-NEXT:    addq %rcx, %r9
; CHECK-NEXT:    vmovq %r9, %xmm0
; CHECK-NEXT:    vmovdqu %ymm0, (%rax)
; CHECK-NEXT:    vzeroupper
; CHECK-NEXT:    retq
  %m = and <8 x i256> %a0, splat (i256 1)
  %r = call i256 @llvm.vector.reduce.add.v8i256(<8 x i256> %m)
  ret i256 %r
}