llvm/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s

define signext i16 @t()   {
; CHECK-LABEL: t:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movswl 0, %eax
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    retl
entry:
	%tmp180 = load i16, ptr null, align 2		; <i16> [#uses=3]
	%tmp180181 = sext i16 %tmp180 to i32		; <i32> [#uses=1]
	%tmp185 = icmp slt i16 %tmp180, 0		; <i1> [#uses=1]
	br i1 %tmp185, label %cond_true188, label %cond_next245

cond_true188:		; preds = %entry
	%tmp195196 = trunc i16 %tmp180 to i8		; <i8> [#uses=0]
	ret i16 0

cond_next245:		; preds = %entry
	%tmp256 = and i32 %tmp180181, 15		; <i32> [#uses=0]
	ret i16 0
}

define signext i16 @t_freeze(ptr %p)   {
; CHECK-LABEL: t_freeze:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT:    movswl (%ecx), %eax
; CHECK-NEXT:    testl %eax, %eax
; CHECK-NEXT:    js .LBB1_1
; CHECK-NEXT:  # %bb.2: # %cond_next
; CHECK-NEXT:    andl $15, %eax
; CHECK-NEXT:    movl %eax, (%ecx)
; CHECK-NEXT:    xorl %eax, %eax
; CHECK-NEXT:    retl
; CHECK-NEXT:  .LBB1_1: # %cond_true
; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
; CHECK-NEXT:    retl
entry:
	%ld = load i16, ptr %p, align 2
	%ld.fr = freeze i16 %ld
	%sext = sext i16 %ld.fr to i32
	%cmp = icmp slt i16 %ld.fr, 0
	br i1 %cmp, label %cond_true, label %cond_next

cond_true:
	ret i16 %ld.fr

cond_next:
	%tmp2 = and i32 %sext, 15
	store i32 %tmp2, ptr %p, align 4
	ret i16 0
}