llvm/test/CodeGen/Thumb2/mve-extbuildvec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s

define arm_aapcs_vfpcc <2 x i64> @zext_v2i1(i1 %a, i1 %b, i1 %c, i1 %d) {
; CHECK-LABEL: zext_v2i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    vldr s1, .LCPI0_0
; CHECK-NEXT:    and r1, r1, #1
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.f32 s3, s1
; CHECK-NEXT:    vmov s2, r1
; CHECK-NEXT:    vmov s0, r0
; CHECK-NEXT:    bx lr
; CHECK-NEXT:    .p2align 2
; CHECK-NEXT:  @ %bb.1:
; CHECK-NEXT:  .LCPI0_0:
; CHECK-NEXT:    .long 0x00000000 @ float 0
  %w = insertelement <2 x i1> poison, i1 %a, i32 0
  %x = insertelement <2 x i1> %w, i1 %b, i32 1
  %s = zext <2 x i1> %x to <2 x i64>
  ret <2 x i64> %s
}

define arm_aapcs_vfpcc <2 x i64> @sext_v2i1(i1 %a, i1 %b, i1 %c, i1 %d) {
; CHECK-LABEL: sext_v2i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r1, r1, #1
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r1, r1, #0
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov q0[2], q0[0], r0, r1
; CHECK-NEXT:    vmov q0[3], q0[1], r0, r1
; CHECK-NEXT:    bx lr
  %w = insertelement <2 x i1> poison, i1 %a, i32 0
  %x = insertelement <2 x i1> %w, i1 %b, i32 1
  %s = sext <2 x i1> %x to <2 x i64>
  ret <2 x i64> %s
}

define arm_aapcs_vfpcc <4 x i32> @zext_v4i1(i1 %a, i1 %b, i1 %c, i1 %d) {
; CHECK-LABEL: zext_v4i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r2, r2, #1
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov q0[2], q0[0], r0, r2
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    and r1, r1, #1
; CHECK-NEXT:    vmov q0[3], q0[1], r1, r0
; CHECK-NEXT:    bx lr
  %w = insertelement <4 x i1> poison, i1 %a, i32 0
  %x = insertelement <4 x i1> %w, i1 %b, i32 1
  %y = insertelement <4 x i1> %x, i1 %c, i32 2
  %z = insertelement <4 x i1> %y, i1 %d, i32 3
  %s = zext <4 x i1> %z to <4 x i32>
  ret <4 x i32> %s
}

define arm_aapcs_vfpcc <4 x i32> @sext_v4i1(i1 %a, i1 %b, i1 %c, i1 %d) {
; CHECK-LABEL: sext_v4i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r2, r2, #1
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r2, r2, #0
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    and r1, r1, #1
; CHECK-NEXT:    vmov q0[2], q0[0], r0, r2
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    rsbs r1, r1, #0
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov q0[3], q0[1], r1, r0
; CHECK-NEXT:    bx lr
  %w = insertelement <4 x i1> poison, i1 %a, i32 0
  %x = insertelement <4 x i1> %w, i1 %b, i32 1
  %y = insertelement <4 x i1> %x, i1 %c, i32 2
  %z = insertelement <4 x i1> %y, i1 %d, i32 3
  %s = sext <4 x i1> %z to <4 x i32>
  ret <4 x i32> %s
}

define arm_aapcs_vfpcc <8 x i16> @zext_v8i1(i1 %a, i1 %b, i1 %c, i1 %d, i1 %e, i1 %f, i1 %g, i1 %h) {
; CHECK-LABEL: zext_v8i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.16 q0[0], r0
; CHECK-NEXT:    and r0, r1, #1
; CHECK-NEXT:    vmov.16 q0[1], r0
; CHECK-NEXT:    and r0, r2, #1
; CHECK-NEXT:    vmov.16 q0[2], r0
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    vmov.16 q0[3], r0
; CHECK-NEXT:    ldr r0, [sp]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.16 q0[4], r0
; CHECK-NEXT:    ldr r0, [sp, #4]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.16 q0[5], r0
; CHECK-NEXT:    ldr r0, [sp, #8]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.16 q0[6], r0
; CHECK-NEXT:    ldr r0, [sp, #12]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.16 q0[7], r0
; CHECK-NEXT:    bx lr
  %w = insertelement <8 x i1> poison, i1 %a, i32 0
  %x = insertelement <8 x i1> %w, i1 %b, i32 1
  %y = insertelement <8 x i1> %x, i1 %c, i32 2
  %z = insertelement <8 x i1> %y, i1 %d, i32 3
  %v = insertelement <8 x i1> %z, i1 %e, i32 4
  %u = insertelement <8 x i1> %v, i1 %f, i32 5
  %t = insertelement <8 x i1> %u, i1 %g, i32 6
  %r = insertelement <8 x i1> %t, i1 %h, i32 7
  %s = zext <8 x i1> %r to <8 x i16>
  ret <8 x i16> %s
}

define arm_aapcs_vfpcc <8 x i16> @sext_v8i1(i1 %a, i1 %b, i1 %c, i1 %d, i1 %e, i1 %f, i1 %g, i1 %h) {
; CHECK-LABEL: sext_v8i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[0], r0
; CHECK-NEXT:    and r0, r1, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[1], r0
; CHECK-NEXT:    and r0, r2, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[2], r0
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[3], r0
; CHECK-NEXT:    ldr r0, [sp]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[4], r0
; CHECK-NEXT:    ldr r0, [sp, #4]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[5], r0
; CHECK-NEXT:    ldr r0, [sp, #8]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[6], r0
; CHECK-NEXT:    ldr r0, [sp, #12]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.16 q0[7], r0
; CHECK-NEXT:    bx lr
  %w = insertelement <8 x i1> poison, i1 %a, i32 0
  %x = insertelement <8 x i1> %w, i1 %b, i32 1
  %y = insertelement <8 x i1> %x, i1 %c, i32 2
  %z = insertelement <8 x i1> %y, i1 %d, i32 3
  %v = insertelement <8 x i1> %z, i1 %e, i32 4
  %u = insertelement <8 x i1> %v, i1 %f, i32 5
  %t = insertelement <8 x i1> %u, i1 %g, i32 6
  %r = insertelement <8 x i1> %t, i1 %h, i32 7
  %s = sext <8 x i1> %r to <8 x i16>
  ret <8 x i16> %s
}

define arm_aapcs_vfpcc <16 x i8> @zext_v16i1(i1 %a, i1 %b, i1 %c, i1 %d, i1 %e, i1 %f, i1 %g, i1 %h, i1 %i, i1 %j, i1 %k, i1 %l, i1 %m, i1 %n, i1 %o, i1 %p) {
; CHECK-LABEL: zext_v16i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[0], r0
; CHECK-NEXT:    and r0, r1, #1
; CHECK-NEXT:    vmov.8 q0[1], r0
; CHECK-NEXT:    and r0, r2, #1
; CHECK-NEXT:    vmov.8 q0[2], r0
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    vmov.8 q0[3], r0
; CHECK-NEXT:    ldr r0, [sp]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[4], r0
; CHECK-NEXT:    ldr r0, [sp, #4]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[5], r0
; CHECK-NEXT:    ldr r0, [sp, #8]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[6], r0
; CHECK-NEXT:    ldr r0, [sp, #12]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[7], r0
; CHECK-NEXT:    ldr r0, [sp, #16]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[8], r0
; CHECK-NEXT:    ldr r0, [sp, #20]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[9], r0
; CHECK-NEXT:    ldr r0, [sp, #24]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[10], r0
; CHECK-NEXT:    ldr r0, [sp, #28]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[11], r0
; CHECK-NEXT:    ldr r0, [sp, #32]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[12], r0
; CHECK-NEXT:    ldr r0, [sp, #36]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[13], r0
; CHECK-NEXT:    ldr r0, [sp, #40]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[14], r0
; CHECK-NEXT:    ldr r0, [sp, #44]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    vmov.8 q0[15], r0
; CHECK-NEXT:    bx lr
  %w = insertelement <16 x i1> poison, i1 %a, i32 0
  %x = insertelement <16 x i1> %w, i1 %b, i32 1
  %y = insertelement <16 x i1> %x, i1 %c, i32 2
  %z = insertelement <16 x i1> %y, i1 %d, i32 3
  %v = insertelement <16 x i1> %z, i1 %e, i32 4
  %u = insertelement <16 x i1> %v, i1 %f, i32 5
  %t = insertelement <16 x i1> %u, i1 %g, i32 6
  %r = insertelement <16 x i1> %t, i1 %h, i32 7
  %w1 = insertelement <16 x i1> %r, i1 %i, i32 8
  %x1 = insertelement <16 x i1> %w1, i1 %j, i32 9
  %y1 = insertelement <16 x i1> %x1, i1 %k, i32 10
  %z1 = insertelement <16 x i1> %y1, i1 %l, i32 11
  %v1 = insertelement <16 x i1> %z1, i1 %m, i32 12
  %u1 = insertelement <16 x i1> %v1, i1 %n, i32 13
  %t1 = insertelement <16 x i1> %u1, i1 %o, i32 14
  %r1 = insertelement <16 x i1> %t1, i1 %p, i32 15
  %s = zext <16 x i1> %r1 to <16 x i8>
  ret <16 x i8> %s
}

define arm_aapcs_vfpcc <16 x i8> @sext_v16i1(i1 %a, i1 %b, i1 %c, i1 %d, i1 %e, i1 %f, i1 %g, i1 %h, i1 %i, i1 %j, i1 %k, i1 %l, i1 %m, i1 %n, i1 %o, i1 %p) {
; CHECK-LABEL: sext_v16i1:
; CHECK:       @ %bb.0:
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[0], r0
; CHECK-NEXT:    and r0, r1, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[1], r0
; CHECK-NEXT:    and r0, r2, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[2], r0
; CHECK-NEXT:    and r0, r3, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[3], r0
; CHECK-NEXT:    ldr r0, [sp]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[4], r0
; CHECK-NEXT:    ldr r0, [sp, #4]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[5], r0
; CHECK-NEXT:    ldr r0, [sp, #8]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[6], r0
; CHECK-NEXT:    ldr r0, [sp, #12]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[7], r0
; CHECK-NEXT:    ldr r0, [sp, #16]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[8], r0
; CHECK-NEXT:    ldr r0, [sp, #20]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[9], r0
; CHECK-NEXT:    ldr r0, [sp, #24]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[10], r0
; CHECK-NEXT:    ldr r0, [sp, #28]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[11], r0
; CHECK-NEXT:    ldr r0, [sp, #32]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[12], r0
; CHECK-NEXT:    ldr r0, [sp, #36]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[13], r0
; CHECK-NEXT:    ldr r0, [sp, #40]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[14], r0
; CHECK-NEXT:    ldr r0, [sp, #44]
; CHECK-NEXT:    and r0, r0, #1
; CHECK-NEXT:    rsbs r0, r0, #0
; CHECK-NEXT:    vmov.8 q0[15], r0
; CHECK-NEXT:    bx lr
  %w = insertelement <16 x i1> poison, i1 %a, i32 0
  %x = insertelement <16 x i1> %w, i1 %b, i32 1
  %y = insertelement <16 x i1> %x, i1 %c, i32 2
  %z = insertelement <16 x i1> %y, i1 %d, i32 3
  %v = insertelement <16 x i1> %z, i1 %e, i32 4
  %u = insertelement <16 x i1> %v, i1 %f, i32 5
  %t = insertelement <16 x i1> %u, i1 %g, i32 6
  %r = insertelement <16 x i1> %t, i1 %h, i32 7
  %w1 = insertelement <16 x i1> %r, i1 %i, i32 8
  %x1 = insertelement <16 x i1> %w1, i1 %j, i32 9
  %y1 = insertelement <16 x i1> %x1, i1 %k, i32 10
  %z1 = insertelement <16 x i1> %y1, i1 %l, i32 11
  %v1 = insertelement <16 x i1> %z1, i1 %m, i32 12
  %u1 = insertelement <16 x i1> %v1, i1 %n, i32 13
  %t1 = insertelement <16 x i1> %u1, i1 %o, i32 14
  %r1 = insertelement <16 x i1> %t1, i1 %p, i32 15
  %s = sext <16 x i1> %r1 to <16 x i8>
  ret <16 x i8> %s
}