llvm/test/CodeGen/RISCV/rvv/sifive-xsfmm-vset-insert.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=riscv64 -mattr=+v \
# RUN:     -run-pass=phi-node-elimination,register-coalescer,riscv-insert-vsetvli | FileCheck %s

--- |
  define void @xsfmm_same_state(<vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 noundef %tm, i64 noundef %tn, i64 noundef %tk) {
  entry:
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)
    ret void
  }

  define void @xsfmm_different_state(<vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk) {
  entry:
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 4)
    ret void
  }

  define void @xsfmm_different_state_bf(<vscale x 32 x half> %tile1, <vscale x 32 x bfloat> %tile2, i64 %tm, i64 %tn, i64 %tk) {
  entry:
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2)
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64 2, <vscale x 32 x bfloat> %tile2, <vscale x 32 x bfloat> %tile2, i64 %tm, i64 %tn, i64 %tk, i64 2)
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 2, <vscale x 32 x half> %tile1, <vscale x 32 x half> %tile1, i64 %tm, i64 %tn, i64 %tk, i64 2)
    ret void
  }

  define <vscale x 64 x i8> @interleave_rvv_and_xsfmm(<vscale x 64 x i8> %tile, i64 %vl, ptr %base) {
  entry:
    %0 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl)
    %1 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %0, i64 %vl)
    call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl)
    ret <vscale x 64 x i8> %1
  }

  define <vscale x 64 x i8> @interleave_rvv_and_xsfmm2(<vscale x 64 x i8> %tile, i64 %vl, ptr %base) {
  entry:
    %0 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %tile, i64 %vl)
    %1 = call <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64 1, i64 %vl)
    %2 = call <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8> poison, <vscale x 64 x i8> %tile, <vscale x 64 x i8> %0, i64 %vl)
    call void @llvm.riscv.sf.vste16.i64(i64 1, ptr %base, i64 %vl)
    ret <vscale x 64 x i8> %2
  }

  define void @consecutive_xsfmm(<vscale x 32 x half> %tile, i64 %tm, i64 %tn, i64 %tk, ptr %base) {
  entry:
    tail call void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64 0, <vscale x 32 x half> %tile, <vscale x 32 x half> %tile, i64 %tm, i64 %tn, i64 %tk, i64 2)
    call void @llvm.riscv.sf.vste16.i64(i64 0, ptr %base, i64 %tn)
    ret void
  }

  define i64 @vsettnt_max(i64 %vl) {
  entry:
    %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2)
    %1 = call i64 @llvm.riscv.sf.vsettnt_max.i64(i64 1, i64 2)
    ret i64 %0
  }

  define i64 @single_vsettm(i64 %vl) {
  entry:
    %0 = call i64 @llvm.riscv.sf.vsettm.i64(i64 %vl, i64 1, i64 2)
    ret i64 %0
  }

  define i64 @single_vsettn(i64 %vl) {
  entry:
    %0 = call i64 @llvm.riscv.sf.vsettn.i64(i64 %vl, i64 1, i64 2)
    ret i64 %0
  }

  define i64 @single_vsettk(i64 %vl) {
  entry:
    %0 = call i64 @llvm.riscv.sf.vsettk.i64(i64 %vl, i64 1, i64 2)
    ret i64 %0
  }

  define void @sf_vtzero(i64 %tm, i64 %tn) {
  entry:
    call void @llvm.riscv.sf.vtzero.i64(i64 1, i64 %tm, i64 %tn, i64 3, i64 4)
    ret void
  }

  declare void @llvm.riscv.sf.mm.f.f.i64.nxv32f16(i64, <vscale x 32 x half>, <vscale x 32 x half>, i64, i64, i64, i64)
  declare void @llvm.riscv.sf.mm.f.f.i64.nxv32bf16(i64, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i64, i64, i64, i64)
  declare <vscale x 64 x i8> @llvm.riscv.sf.vtmv.v.t.nxv64i8.i64(i64, i64)
  declare <vscale x 64 x i8> @llvm.riscv.vadd.nxv64i8.nxv64i8.i64(<vscale x 64 x i8>, <vscale x 64 x i8>, <vscale x 64 x i8>, i64)
  declare void @llvm.riscv.sf.vste16.i64(i64, ptr, i64)
  declare i64 @llvm.riscv.sf.vsettnt_max.i64(i64, i64)
  declare i64 @llvm.riscv.sf.vsettm.i64(i64, i64, i64)
  declare i64 @llvm.riscv.sf.vsettn.i64(i64, i64, i64)
  declare i64 @llvm.riscv.sf.vsettk.i64(i64, i64, i64)
  declare void @llvm.riscv.sf.vtzero.i64(i64, i64, i64, i64, i64)
...
---
name:            xsfmm_same_state
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: vrm8 }
  - { id: 2, class: gprnox0 }
  - { id: 3, class: gprnox0 }
  - { id: 4, class: gprnox0 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$v8m8', virtual-reg: '%1' }
  - { reg: '$x10', virtual-reg: '%2' }
  - { reg: '$x11', virtual-reg: '%3' }
  - { reg: '$x12', virtual-reg: '%4' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-LABEL: name: xsfmm_same_state
    ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET
    %4:gprnox0 = COPY $x12
    %3:gprnox0 = COPY $x11
    %2:gprnox0 = COPY $x10
    %1:vrm8 = COPY $v16m8
    %0:vrm8 = COPY $v8m8
    PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoRET
...
---
name:            xsfmm_different_state
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: vrm8 }
  - { id: 2, class: gprnox0 }
  - { id: 3, class: gprnox0 }
  - { id: 4, class: gprnox0 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$v8m8', virtual-reg: '%1' }
  - { reg: '$x10', virtual-reg: '%2' }
  - { reg: '$x11', virtual-reg: '%3' }
  - { reg: '$x12', virtual-reg: '%4' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-LABEL: name: xsfmm_different_state
    ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1544 /* e16, w4 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 4 /* w4 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET
    %4:gprnox0 = COPY $x12
    %3:gprnox0 = COPY $x11
    %2:gprnox0 = COPY $x10
    %1:vrm8 = COPY $v16m8
    %0:vrm8 = COPY $v8m8
    PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoSF_MM_F_F $t2, %0:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 4, implicit $frm
    PseudoRET
...
---
name:            xsfmm_different_state_bf
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: vrm8 }
  - { id: 2, class: gprnox0 }
  - { id: 3, class: gprnox0 }
  - { id: 4, class: gprnox0 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$v8m8', virtual-reg: '%1' }
  - { reg: '$x10', virtual-reg: '%2' }
  - { reg: '$x11', virtual-reg: '%3' }
  - { reg: '$x12', virtual-reg: '%4' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-LABEL: name: xsfmm_different_state_bf
    ; CHECK: liveins: $v8m8, $v16m8, $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x12
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vrm8 = COPY $v16m8
    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1288 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F_ALT $t2, [[COPY3]], [[COPY3]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY2]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY4]], [[COPY4]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET
    %4:gprnox0 = COPY $x12
    %3:gprnox0 = COPY $x11
    %2:gprnox0 = COPY $x10
    %1:vrm8 = COPY $v16m8
    %0:vrm8 = COPY $v8m8
    PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoSF_MM_F_F_ALT $t2, %1:vrm8, %1:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %2:gprnox0, %3:gprnox0, %4:gprnox0, 4, 2, implicit $frm
    PseudoRET
...
---
name:            interleave_rvv_and_xsfmm
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: gprnox0 }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: vrm8 }
  - { id: 5, class: vrm8 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$x10', virtual-reg: '%1' }
  - { reg: '$x11', virtual-reg: '%2' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $x10, $x11
    ; CHECK-LABEL: name: interleave_rvv_and_xsfmm
    ; CHECK: liveins: $v8m8, $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[PseudoSF_VTMV_V_T]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_]], implicit $vtype
    ; CHECK-NEXT: PseudoRET implicit $v8m8
    %2:gpr = COPY $x11
    %1:gprnox0 = COPY $x10
    %0:vrm8 = COPY $v8m8
    %3:gpr = ADDI $x0, 1
    %4:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1
    %5:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0
    PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1
    $v8m8 = COPY %5:vrm8
    PseudoRET implicit $v8m8
...
---
name:            interleave_rvv_and_xsfmm2
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: gprnox0 }
  - { id: 2, class: gpr }
  - { id: 3, class: gpr }
  - { id: 4, class: vrm8 }
  - { id: 5, class: vrm8 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$x10', virtual-reg: '%1' }
  - { reg: '$x11', virtual-reg: '%2' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $x10, $x11
    ; CHECK-LABEL: name: interleave_rvv_and_xsfmm2
    ; CHECK: liveins: $v8m8, $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
    ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoVADD_VV_M8_:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[COPY2]], [[COPY2]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 512 /* e8, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead [[PseudoSF_VTMV_V_T:%[0-9]+]]:vrm8 = PseudoSF_VTMV_V_T [[ADDI]], $noreg, 3 /* e8 */, 1 /* w1 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY1]], 195 /* e8, m8, ta, ma */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoVADD_VV_M8_1:%[0-9]+]]:vrm8 = PseudoVADD_VV_M8 $noreg, [[PseudoVADD_VV_M8_]], [[PseudoVADD_VV_M8_]], $noreg /* vl */, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: PseudoSF_VSTE16 [[ADDI]], [[COPY]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: $v8m8 = COPY [[PseudoVADD_VV_M8_1]], implicit $vtype
    ; CHECK-NEXT: PseudoRET implicit $v8m8
    %2:gpr = COPY $x11
    %1:gprnox0 = COPY $x10
    %0:vrm8 = COPY $v8m8
    %3:gpr = ADDI $x0, 1
    %4:vrm8 = PseudoVADD_VV_M8 $noreg, %0:vrm8, killed %0:vrm8, %1:gprnox0, 3, 0
    %5:vrm8 = PseudoSF_VTMV_V_T %3:gpr, %1:gprnox0, 3, 1
    %6:vrm8 = PseudoVADD_VV_M8 $noreg, %4:vrm8, killed %4:vrm8, %1:gprnox0, 3, 0
    PseudoSF_VSTE16 %3:gpr, %2:gpr, %1:gprnox0, 4, 1
    $v8m8 = COPY %6:vrm8
    PseudoRET implicit $v8m8
...
---
name:            consecutive_xsfmm
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: vrm8 }
  - { id: 1, class: gprnox0 }
  - { id: 2, class: gprnox0 }
  - { id: 3, class: gprnox0 }
  - { id: 4, class: gprnox0 }
liveins:
  - { reg: '$v8m8', virtual-reg: '%0' }
  - { reg: '$x10', virtual-reg: '%1' }
  - { reg: '$x11', virtual-reg: '%2' }
  - { reg: '$x12', virtual-reg: '%3' }
  - { reg: '$x13', virtual-reg: '%4' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $v8m8, $x10, $x11, $x12, $x13
    ; CHECK-LABEL: name: consecutive_xsfmm
    ; CHECK: liveins: $v8m8, $x10, $x11, $x12, $x13
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vrm8 = COPY $v8m8
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gprnox0 = COPY $x11
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gprnox0 = COPY $x12
    ; CHECK-NEXT: dead [[COPY4:%[0-9]+]]:gprnox0 = COPY $x13
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY2]], 1032 /* e16, w2 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY1]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTK [[COPY3]], 4 /* e16 */, 2 /* w2 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_MM_F_F $t2, [[COPY]], [[COPY]], 7 /* frm=dyn */, $noreg, $noreg, $noreg, 4 /* e16 */, 2 /* w2 */, implicit $frm, implicit $vl, implicit $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY3]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: PseudoSF_VSTE16 [[COPY1]], [[COPY2]], $noreg, 4 /* e16 */, 1 /* w1 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET
    %0:vrm8 = COPY $v8m8
    %1:gprnox0 = COPY $x10
    %2:gprnox0 = COPY $x11
    %3:gprnox0 = COPY $x12
    %4:gprnox0 = COPY $x13
    PseudoSF_MM_F_F $t2, %0:vrm8, %0:vrm8, 7, %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 2, implicit $frm
    PseudoSF_VSTE16 %1:gprnox0, %2:gprnox0, %3:gprnox0, 4, 1
    PseudoRET
...
---
name:            vsettnt_max
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gprnox0 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10
    ; CHECK-LABEL: name: vsettnt_max
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
    ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_1:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
    ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprnox0 = COPY $x10
    %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype
    %2:gprnox0 = PseudoSF_VSETTNTX0 $x0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype
    %3:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype
    $x10 = COPY %3:gprnox0
    PseudoRET implicit $x10
...
---
name:            single_vsettm
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gprnox0 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10
    ; CHECK-LABEL: name: single_vsettm
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoSF_VSETTM:%[0-9]+]]:gprnox0 = PseudoSF_VSETTM [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
    ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTM]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprnox0 = COPY $x10
    %1:gprnox0 = PseudoSF_VSETTM %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype
    $x10 = COPY %1:gprnox0
    PseudoRET implicit $x10
...
---
name:            single_vsettn
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gprnox0 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10
    ; CHECK-LABEL: name: single_vsettn
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[PseudoSF_VSETTNT:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNT [[COPY]], 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTNT]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprnox0 = COPY $x10
    %1:gprnox0 = PseudoSF_VSETTNT %0:gprnox0, 520, implicit-def $vl, implicit-def $vtype, implicit $vtype
    $x10 = COPY %1:gprnox0
    PseudoRET implicit $x10
...
---
name:            single_vsettk
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gprnox0 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10
    ; CHECK-LABEL: name: single_vsettk
    ; CHECK: liveins: $x10
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: dead [[PseudoSF_VSETTNTX0_:%[0-9]+]]:gprnox0 = PseudoSF_VSETTNTX0 killed $x0, 520 /* e16, w1 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: [[PseudoSF_VSETTK:%[0-9]+]]:gprnox0 = PseudoSF_VSETTK [[COPY]], 4 /* e16 */, 1 /* w1 */, implicit-def $vtype, implicit $vtype, implicit $vtype
    ; CHECK-NEXT: $x10 = COPY [[PseudoSF_VSETTK]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:gprnox0 = COPY $x10
    %1:gprnox0 = PseudoSF_VSETTK %0:gprnox0, 4, 1, implicit-def $vtype, implicit $vtype
    $x10 = COPY %1:gprnox0
    PseudoRET implicit $x10
...
---
name:            sf_vtzero
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: gprnox0 }
  - { id: 1, class: gprnox0 }
liveins:
  - { reg: '$x10', virtual-reg: '%0' }
  - { reg: '$x11', virtual-reg: '%1' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10, $x11
    ; CHECK-LABEL: name: sf_vtzero
    ; CHECK: liveins: $x10, $x11
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gprnox0 = COPY $x11
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTNT [[COPY1]], 1536 /* e8, w4 */, implicit-def $vl, implicit-def $vtype
    ; CHECK-NEXT: dead $x0 = PseudoSF_VSETTM [[COPY]], 3 /* e8 */, 4 /* w4 */, implicit-def $vtype, implicit $vtype
    ; CHECK-NEXT: PseudoSF_VTZERO_T $t1, $noreg, $noreg, 3 /* e8 */, 4 /* w4 */, implicit $vl, implicit $vtype
    ; CHECK-NEXT: PseudoRET
    %0:gprnox0 = COPY $x10
    %1:gprnox0 = COPY $x11
    PseudoSF_VTZERO_T $t1, %0:gprnox0, %1:gprnox0, 3, 4
    PseudoRET
...