llvm/test/CodeGen/RISCV/machine-outliner-x5-regsave-rv32e.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+e -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs \
# RUN:   -riscv-outliner-regsave=true < %s | FileCheck -check-prefixes=CHECK %s

--- |
  define i32 @outline_x5_live_0(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_x5_live_1(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_x5_live_2(i32 %a, i32 %b) { ret i32 0 }

  define i32 @outline_no_temp_0(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_no_temp_1(i32 %a, i32 %b) { ret i32 0 }
  define i32 @outline_no_temp_2(i32 %a, i32 %b) { ret i32 0 }
...
---
name:            outline_x5_live_0
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_x5_live_0
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x6 = ADDI $x5, 0
  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11
  ; CHECK-NEXT:   $x5 = ADDI $x6, 0
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...
---
name:            outline_x5_live_1
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_x5_live_1
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x6 = ADDI $x5, 0
  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11
  ; CHECK-NEXT:   $x5 = ADDI $x6, 0
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...
---
name:            outline_x5_live_2
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_x5_live_2
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x6 = ADDI $x5, 0
  ; CHECK-NEXT:   $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x11, implicit-def $x12, implicit-def $x14, implicit $x6, implicit $x10, implicit $x11
  ; CHECK-NEXT:   $x5 = ADDI $x6, 0
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x14
    $x10 = ADD $x14, $x5
    PseudoRET implicit $x10
...
---
name:            outline_no_temp_0
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_no_temp_0
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5, $x6, $x7
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x6, $x7, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   $x10 = ADD $x10, $x6
  ; CHECK-NEXT:   $x10 = ADD $x10, $x7
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5, $x6, $x7
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x6, $x7, $x14
    $x10 = ADD $x14, $x5
    $x10 = ADD $x10, $x6
    $x10 = ADD $x10, $x7
    PseudoRET implicit $x10
...
---
name:            outline_no_temp_1
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_no_temp_1
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5, $x6, $x7
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x6, $x7, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   $x10 = ADD $x10, $x6
  ; CHECK-NEXT:   $x10 = ADD $x10, $x7
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5, $x6, $x7
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x6, $x7, $x14
    $x10 = ADD $x14, $x5
    $x10 = ADD $x10, $x6
    $x10 = ADD $x10, $x7
    PseudoRET implicit $x10
...
---
name:            outline_no_temp_2
tracksRegLiveness: true
body:             |
  ; CHECK-LABEL: name: outline_no_temp_2
  ; CHECK: bb.0:
  ; CHECK-NEXT:   liveins: $x10, $x11, $x5, $x6, $x7
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   $x11 = ANDI $x11, 1023
  ; CHECK-NEXT:   $x12 = ADDI $x10, 17
  ; CHECK-NEXT:   $x11 = AND $x12, $x11
  ; CHECK-NEXT:   $x14 = SUB $x10, $x11
  ; CHECK-NEXT:   PseudoBR %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   liveins: $x5, $x6, $x7, $x14
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $x10 = ADD $x14, $x5
  ; CHECK-NEXT:   $x10 = ADD $x10, $x6
  ; CHECK-NEXT:   $x10 = ADD $x10, $x7
  ; CHECK-NEXT:   PseudoRET implicit $x10
  bb.0:
    liveins: $x10, $x11, $x5, $x6, $x7
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    $x11 = ANDI $x11, 1023
    $x12 = ADDI $x10, 17
    $x11 = AND $x12, $x11
    $x14 = SUB $x10, $x11
    PseudoBR %bb.1

  bb.1:
    liveins: $x5, $x6, $x7, $x14
    $x10 = ADD $x14, $x5
    $x10 = ADD $x10, $x6
    $x10 = ADD $x10, $x7
    PseudoRET implicit $x10
...