llvm/test/CodeGen/AMDGPU/waitcnt-debug-non-first-terminators.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-insert-waitcnts -amdgpu-waitcnt-forcezero=1 %s -o - | FileCheck %s

---
name: waitcnt-debug-non-first-terminators
liveins:
machineFunctionInfo:
  isEntryFunction: true
body:             |
  ; CHECK-LABEL: name: waitcnt-debug-non-first-terminators
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; CHECK-NEXT:   S_BRANCH %bb.2, implicit $scc
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_WAITCNT .Vmcnt_0_Expcnt_0_Lgkmcnt_0
  ; CHECK-NEXT:   S_NOP 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_WAITCNT .Vmcnt_0_Expcnt_0_Lgkmcnt_0
  ; CHECK-NEXT:   S_NOP 0
  bb.0:
    S_CBRANCH_SCC1 %bb.1, implicit $scc
    S_BRANCH %bb.2, implicit $scc
  bb.1:
    S_NOP 0
  bb.2:
    S_NOP 0
...