llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sffbh.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_mov" --version 6
; RUN:  llc -global-isel=0 -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
; RUN:  llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s
; RUN:  llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12PLUS %s
; RUN:  llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1200 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX12PLUS %s

declare i32 @llvm.amdgcn.sffbh.i32(i32) #1

define amdgpu_ps i32 @s_sffbh(i32 inreg %val) {
; GFX8-LABEL: s_sffbh:
; GFX8:  ; %bb.0:
; GFX8:    s_flbit_i32 s0, s0
; GFX8:    ; return to shader part epilog
;
; GFX12PLUS-LABEL: s_sffbh:
; GFX12PLUS:  ; %bb.0:
; GFX12PLUS:    s_cls_i32 s0, s0
; GFX12PLUS:    ; return to shader part epilog
  %r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
  ret i32 %r
}

define amdgpu_ps i32 @v_sffbh(i32 %val) {
; GFX8-LABEL: v_sffbh:
; GFX8:  ; %bb.0:
; GFX8:    v_ffbh_i32_e32 v0, v0
; GFX8:    v_readfirstlane_b32 s0, v0
; GFX8:    ; return to shader part epilog
;
; GFX12PLUS-LABEL: v_sffbh:
; GFX12PLUS:  ; %bb.0:
; GFX12PLUS:    v_cls_i32_e32 v0, v0
; GFX12PLUS:    v_readfirstlane_b32 s0, v0
; GFX12PLUS:    ; return to shader part epilog
  %r = call i32 @llvm.amdgcn.sffbh.i32(i32 %val)
  ret i32 %r
}

attributes #1 = { nounwind readnone }