llvm/test/CodeGen/AMDGPU/insert-skips-gfx1250.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass si-pre-emit-peephole -verify-machineinstrs  %s -o - | FileCheck %s

---
name: skip_wait_xcnt
body: |
  ; CHECK-LABEL: name: skip_wait_xcnt
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   S_CBRANCH_EXECZ %bb.2, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   V_NOP_e32 implicit $exec
  ; CHECK-NEXT:   S_WAIT_XCNT 0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    V_NOP_e32 implicit $exec
    S_WAIT_XCNT 0

  bb.2:
    S_ENDPGM 0
...

---
name: skip_wait_asynccnt
body: |
  ; CHECK-LABEL: name: skip_wait_asynccnt
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   V_NOP_e32 implicit $exec
  ; CHECK-NEXT:   S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    V_NOP_e32 implicit $exec
    S_WAIT_ASYNCCNT 0, implicit $asynccnt, implicit-def $asynccnt

  bb.2:
    S_ENDPGM 0
...