llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: bitreverse_i32_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: bitreverse_i32_s
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:sgpr(s32) = G_BITREVERSE [[COPY]]
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_BITREVERSE %0
...

---
name: bitreverse_i32_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: bitreverse_i32_v
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:vgpr(s32) = G_BITREVERSE [[COPY]]
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_BITREVERSE %0
...

---
name: bitreverse_i64_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: bitreverse_i64_s
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:sgpr(s64) = G_BITREVERSE [[COPY]]
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s64) = G_BITREVERSE %0
...

---
name: bitreverse_i64_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: bitreverse_i64_v
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[BITREVERSE:%[0-9]+]]:vgpr(s64) = G_BITREVERSE [[COPY]]
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_BITREVERSE %0
...