llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-uinc-udec-wrap.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=amdgpu-regbankselect,amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s

# Test G_ATOMICRMW_UINC_WRAP and G_ATOMICRMW_UDEC_WRAP
# register bank selection and legalization for flat, global, and local address spaces.

---
name: atomicrmw_uinc_wrap_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_uinc_wrap_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UINC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UINC_WRAP [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UINC_WRAP]], [[ATOMICRMW_UINC_WRAP]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UINC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_uinc_wrap_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_uinc_wrap_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UINC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UINC_WRAP [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UINC_WRAP]], [[ATOMICRMW_UINC_WRAP]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UINC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_uinc_wrap_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_uinc_wrap_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_UINC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UINC_WRAP [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UINC_WRAP]], [[ATOMICRMW_UINC_WRAP]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_UINC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_udec_wrap_flat_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_udec_wrap_flat_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p0) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UDEC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UDEC_WRAP [[COPY]](p0), [[COPY1]] :: (load store seq_cst (s32))
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UDEC_WRAP]], [[ATOMICRMW_UDEC_WRAP]]
    %0:_(p0) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UDEC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 0)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_udec_wrap_global_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-LABEL: name: atomicrmw_udec_wrap_global_s32_vv
    ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
    ; CHECK-NEXT: [[ATOMICRMW_UDEC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UDEC_WRAP [[COPY]](p1), [[COPY1]] :: (load store seq_cst (s32), addrspace 1)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UDEC_WRAP]], [[ATOMICRMW_UDEC_WRAP]]
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = COPY $vgpr2
    %2:_(s32) = G_ATOMICRMW_UDEC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 1)
    %3:_(s32) = G_AND %2, %2
...

---
name: atomicrmw_udec_wrap_local_s32_vv
legalized: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; CHECK-LABEL: name: atomicrmw_udec_wrap_local_s32_vv
    ; CHECK: liveins: $vgpr0, $vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
    ; CHECK-NEXT: [[ATOMICRMW_UDEC_WRAP:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_UDEC_WRAP [[COPY]](p3), [[COPY1]] :: (load store seq_cst (s32), addrspace 3)
    ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[ATOMICRMW_UDEC_WRAP]], [[ATOMICRMW_UDEC_WRAP]]
    %0:_(p3) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = G_ATOMICRMW_UDEC_WRAP %0, %1 :: (load store seq_cst (s32), addrspace 3)
    %3:_(s32) = G_AND %2, %2
...