llvm/test/CodeGen/AMDGPU/GlobalISel/mad.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -o - %s | FileCheck --check-prefix=GFX7 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -o - %s | FileCheck --check-prefix=GFX90A %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -o - %s | FileCheck --check-prefix=GFX11 %s

define amdgpu_ps void @mad_i64_uniform(i64 inreg %a, i64 inreg %b, ptr addrspace(1) %out) {
; GFX7-LABEL: mad_i64_uniform:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    v_mov_b32_e32 v2, s2
; GFX7-NEXT:    v_mul_hi_u32 v2, s0, v2
; GFX7-NEXT:    s_mul_i32 s4, s0, s2
; GFX7-NEXT:    s_mul_i32 s0, s0, s3
; GFX7-NEXT:    s_mul_i32 s1, s1, s2
; GFX7-NEXT:    v_readfirstlane_b32 s5, v2
; GFX7-NEXT:    s_add_u32 s0, s0, s5
; GFX7-NEXT:    s_add_u32 s5, s1, s0
; GFX7-NEXT:    v_mov_b32_e32 v2, s4
; GFX7-NEXT:    v_mov_b32_e32 v3, s5
; GFX7-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; GFX7-NEXT:    s_endpgm
;
; GFX90A-LABEL: mad_i64_uniform:
; GFX90A:       ; %bb.0:
; GFX90A-NEXT:    s_mul_i32 s4, s0, s2
; GFX90A-NEXT:    s_mul_hi_u32 s5, s0, s2
; GFX90A-NEXT:    s_mul_i32 s0, s0, s3
; GFX90A-NEXT:    s_mul_i32 s1, s1, s2
; GFX90A-NEXT:    s_add_u32 s0, s1, s0
; GFX90A-NEXT:    s_add_i32 s5, s5, s0
; GFX90A-NEXT:    v_pk_mov_b32 v[2:3], s[4:5], s[4:5] op_sel:[0,1]
; GFX90A-NEXT:    global_store_dwordx2 v[0:1], v[2:3], off
; GFX90A-NEXT:    s_endpgm
;
; GFX11-LABEL: mad_i64_uniform:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_mul_hi_u32 s4, s0, s2
; GFX11-NEXT:    s_mul_i32 s3, s0, s3
; GFX11-NEXT:    s_mul_i32 s1, s1, s2
; GFX11-NEXT:    s_add_i32 s3, s4, s3
; GFX11-NEXT:    s_mul_i32 s0, s0, s2
; GFX11-NEXT:    s_add_i32 s1, s3, s1
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT:    global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT:    s_endpgm
  %result = mul i64 %a, %b
  store i64 %result, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @mad_u64_u32_uniform_carry(i32 inreg %a, i32 inreg %b, i64 inreg %c, ptr addrspace(1) %out) {
; GFX7-LABEL: mad_u64_u32_uniform_carry:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    v_mov_b32_e32 v2, s1
; GFX7-NEXT:    v_mul_hi_u32 v2, s0, v2
; GFX7-NEXT:    s_mul_i32 s0, s0, s1
; GFX7-NEXT:    s_add_u32 s0, s0, s2
; GFX7-NEXT:    v_readfirstlane_b32 s1, v2
; GFX7-NEXT:    s_addc_u32 s1, s1, s3
; GFX7-NEXT:    v_mov_b32_e32 v3, s1
; GFX7-NEXT:    v_mov_b32_e32 v2, s0
; GFX7-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]
; GFX7-NEXT:    s_endpgm
;
; GFX90A-LABEL: mad_u64_u32_uniform_carry:
; GFX90A:       ; %bb.0:
; GFX90A-NEXT:    s_mul_i32 s4, s0, s1
; GFX90A-NEXT:    s_mul_hi_u32 s1, s0, s1
; GFX90A-NEXT:    s_add_u32 s0, s4, s2
; GFX90A-NEXT:    s_addc_u32 s1, s1, s3
; GFX90A-NEXT:    v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]
; GFX90A-NEXT:    global_store_dwordx2 v[0:1], v[2:3], off
; GFX90A-NEXT:    s_endpgm
;
; GFX11-LABEL: mad_u64_u32_uniform_carry:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_mul_i32 s4, s0, s1
; GFX11-NEXT:    s_mul_hi_u32 s1, s0, s1
; GFX11-NEXT:    s_add_u32 s0, s4, s2
; GFX11-NEXT:    s_addc_u32 s1, s1, s3
; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT:    v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
; GFX11-NEXT:    global_store_b64 v[0:1], v[2:3], off
; GFX11-NEXT:    s_endpgm
  %a.ext = zext i32 %a to i64
  %b.ext = zext i32 %b to i64
  %mul = mul i64 %a.ext, %b.ext
  %result = add i64 %mul, %c
  store i64 %result, ptr addrspace(1) %out
  ret void
}

define amdgpu_ps void @mad_i64_div(i64 %a, i64 %b, ptr addrspace(1) %out) {
; GFX7-LABEL: mad_i64_div:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], v0, v2, 0
; GFX7-NEXT:    v_mad_u64_u32 v[9:10], s[0:1], v0, v3, v[7:8]
; GFX7-NEXT:    v_mad_u64_u32 v[7:8], s[0:1], v1, v2, v[9:10]
; GFX7-NEXT:    flat_store_dwordx2 v[4:5], v[6:7]
; GFX7-NEXT:    s_endpgm
;
; GFX90A-LABEL: mad_i64_div:
; GFX90A:       ; %bb.0:
; GFX90A-NEXT:    v_mad_u64_u32 v[8:9], s[0:1], v0, v3, 0
; GFX90A-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], v0, v2, 0
; GFX90A-NEXT:    v_mad_u64_u32 v[10:11], s[0:1], v1, v2, v[8:9]
; GFX90A-NEXT:    v_add_u32_e32 v7, v7, v10
; GFX90A-NEXT:    global_store_dwordx2 v[4:5], v[6:7], off
; GFX90A-NEXT:    s_endpgm
;
; GFX11-LABEL: mad_i64_div:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    v_mad_u64_u32 v[6:7], null, v0, v2, 0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_mad_u64_u32 v[9:10], null, v0, v3, v[7:8]
; GFX11-NEXT:    v_mad_u64_u32 v[7:8], null, v1, v2, v[9:10]
; GFX11-NEXT:    global_store_b64 v[4:5], v[6:7], off
; GFX11-NEXT:    s_endpgm
  %result = mul i64 %a, %b
  store i64 %result, ptr addrspace(1) %out
  ret void
}