llvm/test/CodeGen/AArch64/sve2p2-intrinsics-fp-converts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p2 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p2 -force-streaming < %s | FileCheck %s


;FCVTNT, BFCVTNT
define <vscale x 8 x half> @fcvtnt_f16_f32_z(<vscale x 8 x half> %even, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
; CHECK-LABEL: fcvtnt_f16_f32_z:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtnt z0.h, p0/z, z1.s
; CHECK-NEXT:    ret
  %out = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtnt.z.f16f32(<vscale x 8 x half> %even,
		                                                    <vscale x 4 x i1> %pg,
                                                                    <vscale x 4 x float> %b)
  ret <vscale x 8 x half> %out
}

define <vscale x 8 x bfloat> @fcvtnt_bf16_f32_z(<vscale x 8 x bfloat> %even, <vscale x 4 x i1> %pg, <vscale x 4 x float> %b) {
; CHECK-LABEL: fcvtnt_bf16_f32_z:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bfcvtnt z0.h, p0/z, z1.s
; CHECK-NEXT:    ret
  %out = call <vscale x 8 x bfloat> @llvm.aarch64.sve.fcvtnt.z.bf16f32(<vscale x 8 x bfloat> %even,
                                                                       <vscale x 4 x i1> %pg,
                                                                       <vscale x 4 x float> %b)
  ret <vscale x 8 x bfloat> %out
}

define <vscale x 4 x float> @fcvtnt_f32_f64_z(<vscale x 4 x float> %even, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
; CHECK-LABEL: fcvtnt_f32_f64_z:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtnt z0.s, p0/z, z1.d
; CHECK-NEXT:    ret
  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtnt.z.f32f64(<vscale x 4 x float> %even,
		                                                     <vscale x 2 x i1> %pg,
                                                                     <vscale x 2 x double> %b)
  ret <vscale x 4 x float> %out
}

;FCVTXNT


define <vscale x 4 x float> @fcvtxnt_f32_f64_z(<vscale x 4 x float> %a, <vscale x 2 x i1> %pg, <vscale x 2 x double> %b) {
; CHECK-LABEL: fcvtxnt_f32_f64_z:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtxnt z0.s, p0/z, z1.d
; CHECK-NEXT:    ret
  %out = call <vscale x 4 x float> @llvm.aarch64.sve.fcvtxnt.z.f32f64(<vscale x 4 x float> %a,
                                                                      <vscale x 2 x i1> %pg,
                                                                      <vscale x 2 x double> %b)
  ret <vscale x 4 x float> %out
}