llvm/test/CodeGen/AArch64/sve-fixed-vector-extract-256-bits.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -aarch64-sve-vector-bits-min=256 -aarch64-sve-vector-bits-max=256 < %s -o - | FileCheck %s

; Note: This test case is reduced from: https://github.com/llvm/llvm-project/pull/166748#issuecomment-3600498185

define i32 @test_extract_v8i32_from_nxv8i32(<vscale x 8 x i32> %vec) nounwind {
; CHECK-LABEL: test_extract_v8i32_from_nxv8i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT:    addvl sp, sp, #-2
; CHECK-NEXT:    str z0, [sp]
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    ldr z0, [sp]
; CHECK-NEXT:    str z1, [sp, #1, mul vl]
; CHECK-NEXT:    uaddv d0, p0, z0.s
; CHECK-NEXT:    fmov w0, s0
; CHECK-NEXT:    addvl sp, sp, #2
; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT:    ret
  %1 = tail call <8 x i32> @llvm.vector.extract.v8i32.nxv8i32(<vscale x 8 x i32> %vec, i64 0)
  %2 = tail call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %1)
  ret i32 %2
}