llvm/test/CodeGen/AArch64/pr161013.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-- < %s | FileCheck %s

define <16 x i4> @avir_v2i4_v16i4(<2 x i4> %arg) nounwind {
; CHECK-LABEL: avir_v2i4_v16i4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sub sp, sp, #16
; CHECK-NEXT:    uzp1 v1.4h, v0.4h, v0.4h
; CHECK-NEXT:    movi v0.2d, #0000000000000000
; CHECK-NEXT:    fmov x8, d1
; CHECK-NEXT:    and w9, w8, #0xf
; CHECK-NEXT:    mov v0.b[0], w9
; CHECK-NEXT:    ubfx w9, w8, #4, #4
; CHECK-NEXT:    mov v0.b[1], w9
; CHECK-NEXT:    ubfx w9, w8, #8, #4
; CHECK-NEXT:    mov v0.b[2], w9
; CHECK-NEXT:    ubfx w9, w8, #12, #4
; CHECK-NEXT:    mov v0.b[3], w9
; CHECK-NEXT:    ubfx w9, w8, #16, #4
; CHECK-NEXT:    mov v0.b[4], w9
; CHECK-NEXT:    ubfx w9, w8, #20, #4
; CHECK-NEXT:    mov v0.b[5], w9
; CHECK-NEXT:    ubfx w9, w8, #24, #4
; CHECK-NEXT:    mov v0.b[6], w9
; CHECK-NEXT:    lsr w9, w8, #28
; CHECK-NEXT:    mov v0.b[7], w9
; CHECK-NEXT:    ubfx x9, x8, #32, #4
; CHECK-NEXT:    mov v0.b[8], w9
; CHECK-NEXT:    ubfx x9, x8, #36, #4
; CHECK-NEXT:    mov v0.b[9], w9
; CHECK-NEXT:    ubfx x9, x8, #40, #4
; CHECK-NEXT:    mov v0.b[10], w9
; CHECK-NEXT:    ubfx x9, x8, #44, #4
; CHECK-NEXT:    mov v0.b[11], w9
; CHECK-NEXT:    ubfx x9, x8, #52, #4
; CHECK-NEXT:    mov v0.b[13], w9
; CHECK-NEXT:    ubfx x9, x8, #56, #4
; CHECK-NEXT:    lsr x8, x8, #60
; CHECK-NEXT:    mov v0.b[14], w9
; CHECK-NEXT:    mov v0.b[15], w8
; CHECK-NEXT:    add sp, sp, #16
; CHECK-NEXT:    ret
  %res = shufflevector <2 x i4> %arg, <2 x i4> poison,
  <16 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 1     , i32 poison, i32 poison, i32 poison,
              i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
  ret <16 x i4> %res
}