llvm/test/CodeGen/AArch64/vecreduce-add-vector.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK-SD
; RUN: llc -mtriple=aarch64-none-linux-gnu -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK-GI

define <4 x i16> @reduce_add_v8i8_zext_ret_v4i16(<8 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v8i8_zext_ret_v4i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv h0, v0.8b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i8_zext_ret_v4i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv h0, v0.8b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <8 x i8> %x to <8 x i16>
  %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
  %t2 = insertelement <4 x i16> zeroinitializer, i16 %z, i64 0
  ret <4 x i16> %t2
}

define <8 x i16> @reduce_add_v8i8_zext_ret_v8i16(<8 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v8i8_zext_ret_v8i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv h0, v0.8b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i8_zext_ret_v8i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv h0, v0.8b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    mov v0.h[4], wzr
; CHECK-GI-NEXT:    mov v0.h[5], wzr
; CHECK-GI-NEXT:    mov v0.h[6], wzr
; CHECK-GI-NEXT:    mov v0.h[7], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <8 x i8> %x to <8 x i16>
  %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
  %t2 = insertelement <8 x i16> zeroinitializer, i16 %z, i64 0
  ret <8 x i16> %t2
}

define <4 x i16> @reduce_add_v16i8_zext_ret_v4i16(<16 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v16i8_zext_ret_v4i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv h0, v0.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v16i8_zext_ret_v4i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv h0, v0.16b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <16 x i8> %x to <16 x i16>
  %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
  %t2 = insertelement <4 x i16> zeroinitializer, i16 %z, i64 0
  ret <4 x i16> %t2
}

define <8 x i16> @reduce_add_v16i8_zext_ret_v8i16(<16 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v16i8_zext_ret_v8i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv h0, v0.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v16i8_zext_ret_v8i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv h0, v0.16b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    mov v0.h[4], wzr
; CHECK-GI-NEXT:    mov v0.h[5], wzr
; CHECK-GI-NEXT:    mov v0.h[6], wzr
; CHECK-GI-NEXT:    mov v0.h[7], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <16 x i8> %x to <16 x i16>
  %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
  %t2 = insertelement <8 x i16> zeroinitializer, i16 %z, i64 0
  ret <8 x i16> %t2
}

define <2 x i32> @reduce_add_v4i16_zext_ret_v2i32(<4 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v4i16_zext_ret_v2i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv s0, v0.4h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i16_zext_ret_v2i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv s0, v0.4h
; CHECK-GI-NEXT:    mov v0.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <4 x i16> %x to <4 x i32>
  %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
  %t2 = insertelement <2 x i32> zeroinitializer, i32 %z, i64 0
  ret <2 x i32> %t2
}

define <4 x i32> @reduce_add_v4i16_zext_ret_v4i32(<4 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v4i16_zext_ret_v4i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv s0, v0.4h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i16_zext_ret_v4i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv s0, v0.4h
; CHECK-GI-NEXT:    mov s0, v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    mov v0.s[2], wzr
; CHECK-GI-NEXT:    mov v0.s[3], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <4 x i16> %x to <4 x i32>
  %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
  %t2 = insertelement <4 x i32> zeroinitializer, i32 %z, i64 0
  ret <4 x i32> %t2
}

define <2 x i32> @reduce_add_v8i16_zext_ret_v2i32(<8 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v8i16_zext_ret_v2i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv s0, v0.8h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i16_zext_ret_v2i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv s0, v0.8h
; CHECK-GI-NEXT:    mov v0.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <8 x i16> %x to <8 x i32>
  %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
  %t2 = insertelement <2 x i32> zeroinitializer, i32 %z, i64 0
  ret <2 x i32> %t2
}

define <4 x i32> @reduce_add_v8i16_zext_ret_v4i32(<8 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v8i16_zext_ret_v4i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv s0, v0.8h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i16_zext_ret_v4i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv s0, v0.8h
; CHECK-GI-NEXT:    mov s0, v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    mov v0.s[2], wzr
; CHECK-GI-NEXT:    mov v0.s[3], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <8 x i16> %x to <8 x i32>
  %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
  %t2 = insertelement <4 x i32> zeroinitializer, i32 %z, i64 0
  ret <4 x i32> %t2
}

define <1 x i64> @reduce_add_v4i32_zext_ret_v1i64(<4 x i32> %x) {
; CHECK-SD-LABEL: reduce_add_v4i32_zext_ret_v1i64:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv d0, v0.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i32_zext_ret_v1i64:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv d0, v0.4s
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <4 x i32> %x to <4 x i64>
  %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
  %t2 = insertelement <1 x i64> zeroinitializer, i64 %z, i64 0
  ret <1 x i64> %t2
}

define <2 x i64> @reduce_add_v4i32_zext_ret_v2i64(<4 x i32> %x) {
; CHECK-SD-LABEL: reduce_add_v4i32_zext_ret_v2i64:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    uaddlv d0, v0.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i32_zext_ret_v2i64:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    uaddlv d0, v0.4s
; CHECK-GI-NEXT:    mov d0, v0.d[0]
; CHECK-GI-NEXT:    mov v0.d[1], xzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = zext <4 x i32> %x to <4 x i64>
  %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
  %t2 = insertelement <2 x i64> zeroinitializer, i64 %z, i64 0
  ret <2 x i64> %t2
}

define <4 x i16> @reduce_add_v8i8_sext_ret_v4i16(<8 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v8i8_sext_ret_v4i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv h0, v0.8b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i8_sext_ret_v4i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv h0, v0.8b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <8 x i8> %x to <8 x i16>
  %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
  %t2 = insertelement <4 x i16> zeroinitializer, i16 %z, i64 0
  ret <4 x i16> %t2
}

define <8 x i16> @reduce_add_v8i8_sext_ret_v8i16(<8 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v8i8_sext_ret_v8i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv h0, v0.8b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i8_sext_ret_v8i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv h0, v0.8b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    mov v0.h[4], wzr
; CHECK-GI-NEXT:    mov v0.h[5], wzr
; CHECK-GI-NEXT:    mov v0.h[6], wzr
; CHECK-GI-NEXT:    mov v0.h[7], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <8 x i8> %x to <8 x i16>
  %z = call i16 @llvm.vector.reduce.add.v8i16(<8 x i16> %xx)
  %t2 = insertelement <8 x i16> zeroinitializer, i16 %z, i64 0
  ret <8 x i16> %t2
}

define <4 x i16> @reduce_add_v16i8_sext_ret_v4i16(<16 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v16i8_sext_ret_v4i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv h0, v0.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v16i8_sext_ret_v4i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv h0, v0.16b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <16 x i8> %x to <16 x i16>
  %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
  %t2 = insertelement <4 x i16> zeroinitializer, i16 %z, i64 0
  ret <4 x i16> %t2
}

define <8 x i16> @reduce_add_v16i8_sext_ret_v8i16(<16 x i8> %x) {
; CHECK-SD-LABEL: reduce_add_v16i8_sext_ret_v8i16:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv h0, v0.16b
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v16i8_sext_ret_v8i16:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv h0, v0.16b
; CHECK-GI-NEXT:    mov v0.h[1], wzr
; CHECK-GI-NEXT:    mov v0.h[2], wzr
; CHECK-GI-NEXT:    mov v0.h[3], wzr
; CHECK-GI-NEXT:    mov v0.h[4], wzr
; CHECK-GI-NEXT:    mov v0.h[5], wzr
; CHECK-GI-NEXT:    mov v0.h[6], wzr
; CHECK-GI-NEXT:    mov v0.h[7], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <16 x i8> %x to <16 x i16>
  %z = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %xx)
  %t2 = insertelement <8 x i16> zeroinitializer, i16 %z, i64 0
  ret <8 x i16> %t2
}

define <2 x i32> @reduce_add_v4i16_sext_ret_v2i32(<4 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v4i16_sext_ret_v2i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv s0, v0.4h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i16_sext_ret_v2i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv s0, v0.4h
; CHECK-GI-NEXT:    mov v0.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <4 x i16> %x to <4 x i32>
  %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
  %t2 = insertelement <2 x i32> zeroinitializer, i32 %z, i64 0
  ret <2 x i32> %t2
}

define <4 x i32> @reduce_add_v4i16_sext_ret_v4i32(<4 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v4i16_sext_ret_v4i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv s0, v0.4h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i16_sext_ret_v4i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv s0, v0.4h
; CHECK-GI-NEXT:    mov s0, v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    mov v0.s[2], wzr
; CHECK-GI-NEXT:    mov v0.s[3], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <4 x i16> %x to <4 x i32>
  %z = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %xx)
  %t2 = insertelement <4 x i32> zeroinitializer, i32 %z, i64 0
  ret <4 x i32> %t2
}

define <2 x i32> @reduce_add_v8i16_sext_ret_v2i32(<8 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v8i16_sext_ret_v2i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv s0, v0.8h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i16_sext_ret_v2i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv s0, v0.8h
; CHECK-GI-NEXT:    mov v0.s[0], v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <8 x i16> %x to <8 x i32>
  %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
  %t2 = insertelement <2 x i32> zeroinitializer, i32 %z, i64 0
  ret <2 x i32> %t2
}

define <4 x i32> @reduce_add_v8i16_sext_ret_v4i32(<8 x i16> %x) {
; CHECK-SD-LABEL: reduce_add_v8i16_sext_ret_v4i32:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv s0, v0.8h
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v8i16_sext_ret_v4i32:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv s0, v0.8h
; CHECK-GI-NEXT:    mov s0, v0.s[0]
; CHECK-GI-NEXT:    mov v0.s[1], wzr
; CHECK-GI-NEXT:    mov v0.s[2], wzr
; CHECK-GI-NEXT:    mov v0.s[3], wzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <8 x i16> %x to <8 x i32>
  %z = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %xx)
  %t2 = insertelement <4 x i32> zeroinitializer, i32 %z, i64 0
  ret <4 x i32> %t2
}

define <1 x i64> @reduce_add_v4i32_sext_ret_v1i64(<4 x i32> %x) {
; CHECK-SD-LABEL: reduce_add_v4i32_sext_ret_v1i64:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv d0, v0.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i32_sext_ret_v1i64:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv d0, v0.4s
; CHECK-GI-NEXT:    // kill: def $d0 killed $d0 killed $q0
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <4 x i32> %x to <4 x i64>
  %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
  %t2 = insertelement <1 x i64> zeroinitializer, i64 %z, i64 0
  ret <1 x i64> %t2
}

define <2 x i64> @reduce_add_v4i32_sext_ret_v2i64(<4 x i32> %x) {
; CHECK-SD-LABEL: reduce_add_v4i32_sext_ret_v2i64:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    saddlv d0, v0.4s
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: reduce_add_v4i32_sext_ret_v2i64:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    saddlv d0, v0.4s
; CHECK-GI-NEXT:    mov d0, v0.d[0]
; CHECK-GI-NEXT:    mov v0.d[1], xzr
; CHECK-GI-NEXT:    ret
entry:
  %xx = sext <4 x i32> %x to <4 x i64>
  %z = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %xx)
  %t2 = insertelement <2 x i64> zeroinitializer, i64 %z, i64 0
  ret <2 x i64> %t2
}