llvm/test/CodeGen/ARM/pr159343.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -mtriple=thumbv7-unknown-linux-android29 %s -o - | FileCheck %s
---
name: Test_shouldRewriteCopySrc_Invalid_SubReg
tracksRegLiveness: true
body:             |
  bb.1:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: Test_shouldRewriteCopySrc_Invalid_SubReg
    ; CHECK: liveins: $r0, $r1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:dpair = IMPLICIT_DEF
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:dpr_vfp2 = COPY [[DEF]].dsub_0
    ; CHECK-NEXT: [[VMOVRRD:%[0-9]+]]:gpr, [[VMOVRRD1:%[0-9]+]]:gpr = VMOVRRD [[COPY]], 14 /* CC::al */, $noreg
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:spr = COPY [[COPY]].ssub_1
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:spr = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:spr = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF3:%[0-9]+]]:spr = IMPLICIT_DEF
    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:mqpr = REG_SEQUENCE killed [[DEF2]], %subreg.ssub_0, killed [[DEF1]], %subreg.ssub_1, killed [[DEF3]], %subreg.ssub_2, [[COPY]].ssub_1, %subreg.ssub_3
    ; CHECK-NEXT: VST1q64 $r1, 0, killed [[REG_SEQUENCE]], 14 /* CC::al */, $noreg
    %0:dpair = IMPLICIT_DEF
    %1:dpr = COPY %0.dsub_0
    %2:gpr, %3:gpr = VMOVRRD killed %1, 14 /* CC::al */, $noreg
    %4:spr = VMOVSR killed %3, 14 /* CC::al */, $noreg
    %5:spr = IMPLICIT_DEF
    %6:spr = IMPLICIT_DEF
    %7:spr = IMPLICIT_DEF
    %8:mqpr = REG_SEQUENCE killed %6, %subreg.ssub_0, killed %5, %subreg.ssub_1, killed %7, %subreg.ssub_2, killed %4, %subreg.ssub_3
    VST1q64 $r1, 0, killed %8, 14 /* CC::al */, $noreg
...