llvm/test/CodeGen/Mips/llvm-ir/two-consecutive-mult.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=mips -mcpu=mips2 -O3 -relocation-model=pic \
; RUN:   -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS2
; RUN: llc < %s -mtriple=mips -mcpu=mips32 -O3 -relocation-model=pic \
; RUN:   -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS32

; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -O3 -relocation-model=pic \
; RUN:   -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS3
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -O3 -relocation-model=pic \
; RUN:   -mips-jalr-reloc=false | FileCheck %s -check-prefixes=MIPS64

define signext i32 @mult_i32(i32 signext %a, i32 signext %b, i32 signext %c) {
; MIPS2-LABEL: mult_i32:
; MIPS2:       # %bb.0: # %entry
; MIPS2-NEXT:    mult $4, $5
; MIPS2-NEXT:    mflo $1
; MIPS2-NEXT:    nop
; MIPS2-NEXT:    nop
; MIPS2-NEXT:    mult $1, $6
; MIPS2-NEXT:    mflo $2
; MIPS2-NEXT:    jr $ra
; MIPS2-NEXT:    nop
;
; MIPS32-LABEL: mult_i32:
; MIPS32:       # %bb.0: # %entry
; MIPS32-NEXT:    mul $1, $4, $5
; MIPS32-NEXT:    jr $ra
; MIPS32-NEXT:    mul $2, $1, $6
;
entry:
  %mul = mul nsw i32 %a, %b
  %mul1 = mul nsw i32 %mul, %c
  ret i32 %mul1
}

define signext i64 @mul_i64(i64 signext %a, i64 signext %b, i64 signext %c) {
; MIPS3-LABEL: mul_i64:
; MIPS3:       # %bb.0: # %entry
; MIPS3-NEXT:    dmult $4, $5
; MIPS3-NEXT:    mflo $1
; MIPS3-NEXT:    nop
; MIPS3-NEXT:    nop
; MIPS3-NEXT:    dmult $1, $6
; MIPS3-NEXT:    mflo $2
; MIPS3-NEXT:    jr $ra
; MIPS3-NEXT:    nop
;
; MIPS64-LABEL: mul_i64:
; MIPS64:       # %bb.0: # %entry
; MIPS64-NEXT:    dmult $4, $5
; MIPS64-NEXT:    mflo $1
; MIPS64-NEXT:    dmult $1, $6
; MIPS64-NEXT:    jr $ra
; MIPS64-NEXT:    mflo $2
;
entry:
  %mul = mul i64 %a, %b
  %mul1 = mul i64 %mul, %c
  ret i64 %mul1
}