llvm/test/CodeGen/AMDGPU/dbg-value-starts-sched-region.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -verify-misched -run-pass=machine-scheduler -o - %s | FileCheck %s

# Verify we maintain live-ins even if the first instruction in sched region is
# DBG_.

---
name:            sched
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK-LABEL: name: sched
    ; CHECK: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: SCHED_BARRIER 0
    ; CHECK-NEXT: DBG_VALUE
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:sgpr_32 = COPY [[DEF]]
    ; CHECK-NEXT: S_NOP 0
    ; CHECK-NEXT: S_ENDPGM 0
    %0:sgpr_32 = IMPLICIT_DEF
    S_NOP 0
    SCHED_BARRIER 0
    DBG_VALUE
    dead %1:sgpr_32 = COPY %0
    S_NOP 0
    S_ENDPGM 0
...