llvm/test/CodeGen/AArch64/peephole-csel.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -o - -mtriple=aarch64-unknown-linux -run-pass=aarch64-mi-peephole-opt -verify-machineinstrs | FileCheck %s

---
name:            peephole_cselxr_same
registers:
  - { id: 1, class: gpr64, preferred-register: '' }
  - { id: 2, class: gpr64, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%1' }
  - { reg: '$x1', virtual-reg: '%2' }
body:             |
  bb.0.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: peephole_cselxr_same
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
    ; CHECK-NEXT: [[ORRXrs:%[0-9]+]]:gpr64 = ORRXrs $xzr, [[COPY1]], 0
    ; CHECK-NEXT: RET_ReallyLR
    %3:gpr64 = COPY $x1
    %4:gpr64 = COPY $x0
    $xzr = ANDSXri %3, 0, implicit-def $nzcv
    %5:gpr64 = CSELXr %4, %4, 0, implicit $nzcv
    RET_ReallyLR

...
---
name:            peephole_cselwr_same
registers:
  - { id: 1, class: gpr32, preferred-register: '' }
  - { id: 2, class: gpr32, preferred-register: '' }
liveins:
  - { reg: '$w0', virtual-reg: '%1' }
  - { reg: '$w1', virtual-reg: '%2' }
body:             |
  bb.0.entry:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: peephole_cselwr_same
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
    ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY1]], 0
    ; CHECK-NEXT: RET_ReallyLR
    %3:gpr32 = COPY $w1
    %4:gpr32 = COPY $w0
    $wzr = ANDSWri %3, 0, implicit-def $nzcv
    %5:gpr32 = CSELWr %4, %4, 0, implicit $nzcv
    RET_ReallyLR

...
---
name:            peephole_cselxr_different
registers:
  - { id: 1, class: gpr64, preferred-register: '' }
  - { id: 2, class: gpr64, preferred-register: '' }
liveins:
  - { reg: '$x0', virtual-reg: '%1' }
  - { reg: '$x1', virtual-reg: '%2' }
body:             |
  bb.0.entry:
    liveins: $x0, $x1

    ; CHECK-LABEL: name: peephole_cselxr_different
    ; CHECK: liveins: $x0, $x1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
    ; CHECK-NEXT: $xzr = ANDSXri [[COPY]], 0, implicit-def $nzcv
    ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY]], [[COPY1]], 0, implicit $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %3:gpr64 = COPY $x1
    %4:gpr64 = COPY $x0
    $xzr = ANDSXri %3, 0, implicit-def $nzcv
    %5:gpr64 = CSELXr %3, %4, 0, implicit $nzcv
    RET_ReallyLR

...
---
name:            peephole_cselwr_different
registers:
  - { id: 1, class: gpr32, preferred-register: '' }
  - { id: 2, class: gpr32, preferred-register: '' }
liveins:
  - { reg: '$w0', virtual-reg: '%1' }
  - { reg: '$w1', virtual-reg: '%2' }
body:             |
  bb.0.entry:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: peephole_cselwr_different
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
    ; CHECK-NEXT: $wzr = ANDSWri [[COPY]], 0, implicit-def $nzcv
    ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY1]], 0, implicit $nzcv
    ; CHECK-NEXT: RET_ReallyLR
    %3:gpr32 = COPY $w1
    %4:gpr32 = COPY $w0
    $wzr = ANDSWri %3, 0, implicit-def $nzcv
    %5:gpr32 = CSELWr %3, %4, 0, implicit $nzcv
    RET_ReallyLR

...