llvm/test/CodeGen/AMDGPU/lower-intrinsics-cluster-barrier.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=0 | FileCheck --check-prefixes=CHECK,NOOPT %s
; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=1 -mattr=+wavefrontsize32 | FileCheck --check-prefixes=CHECK,OPT-WAVE32 %s
; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -codegen-opt-level=1 -mattr=+wavefrontsize64 | FileCheck --check-prefixes=CHECK,OPT-WAVE64 %s

declare void @foo(i1)

; Verify that the explicit use of a split cluster barrier isn't optimized away.
define amdgpu_kernel void @split_barriers() "amdgpu-flat-work-group-size"="32,32" {
; CHECK-LABEL: define amdgpu_kernel void @split_barriers(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; CHECK-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; CHECK-NEXT:    [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -3)
; CHECK-NEXT:    call void @foo(i1 [[ISFIRST]])
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.s.barrier.signal(i32 -3)
  call void @llvm.amdgcn.s.barrier.wait(i16 -3)
  %isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -3)
  call void @foo(i1 %isfirst)
  ret void
}

define amdgpu_kernel void @s_cluster_barrier() {
; CHECK-LABEL: define amdgpu_kernel void @s_cluster_barrier(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
; CHECK-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -1)
; CHECK-NEXT:    br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]
; CHECK:       [[BB2]]:
; CHECK-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; CHECK-NEXT:    br label %[[BB3]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; CHECK-NEXT:    ret void
;
  call void @llvm.amdgcn.s.cluster.barrier()
  ret void
}

define amdgpu_kernel void @s_cluster_barrier_wg32() "amdgpu-flat-work-group-size"="32,32" {
; NOOPT-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(
; NOOPT-SAME: ) #[[ATTR1]] {
; NOOPT-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -1)
; NOOPT-NEXT:    br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]
; NOOPT:       [[BB2]]:
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; NOOPT-NEXT:    br label %[[BB3]]
; NOOPT:       [[BB3]]:
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; NOOPT-NEXT:    ret void
;
; OPT-WAVE32-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(
; OPT-WAVE32-SAME: ) #[[ATTR1]] {
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.wave.barrier()
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; OPT-WAVE32-NEXT:    ret void
;
; OPT-WAVE64-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg32(
; OPT-WAVE64-SAME: ) #[[ATTR1]] {
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.wave.barrier()
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; OPT-WAVE64-NEXT:    ret void
;
  call void @llvm.amdgcn.s.cluster.barrier()
  ret void
}

define amdgpu_kernel void @s_cluster_barrier_wg64() "amdgpu-flat-work-group-size"="64,64" {
; NOOPT-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(
; NOOPT-SAME: ) #[[ATTR2:[0-9]+]] {
; NOOPT-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -1)
; NOOPT-NEXT:    br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]
; NOOPT:       [[BB2]]:
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; NOOPT-NEXT:    br label %[[BB3]]
; NOOPT:       [[BB3]]:
; NOOPT-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; NOOPT-NEXT:    ret void
;
; OPT-WAVE32-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(
; OPT-WAVE32-SAME: ) #[[ATTR2:[0-9]+]] {
; OPT-WAVE32-NEXT:    [[TMP1:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -1)
; OPT-WAVE32-NEXT:    br i1 [[TMP1]], label %[[BB2:.*]], label %[[BB3:.*]]
; OPT-WAVE32:       [[BB2]]:
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; OPT-WAVE32-NEXT:    br label %[[BB3]]
; OPT-WAVE32:       [[BB3]]:
; OPT-WAVE32-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; OPT-WAVE32-NEXT:    ret void
;
; OPT-WAVE64-LABEL: define amdgpu_kernel void @s_cluster_barrier_wg64(
; OPT-WAVE64-SAME: ) #[[ATTR2:[0-9]+]] {
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.wave.barrier()
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.s.barrier.signal(i32 -3)
; OPT-WAVE64-NEXT:    call void @llvm.amdgcn.s.barrier.wait(i16 -3)
; OPT-WAVE64-NEXT:    ret void
;
  call void @llvm.amdgcn.s.cluster.barrier()
  ret void
}