llvm/test/CodeGen/AMDGPU/hazard-gfx1250-flat-scr-hi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass si-fold-operands %s -o - | FileCheck -check-prefix=GCN %s

---
name:            s_ashr_i64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_ashr_i64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_ASHR_I64_:%[0-9]+]]:sreg_64 = S_ASHR_I64 [[DEF]], [[COPY]], implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_ASHR_I64 %1:sreg_64, %0, implicit-def $scc
...

---
name:            s_lshl_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_lshl_b64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[DEF]], [[COPY]], implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_LSHL_B64 %1:sreg_64, %0, implicit-def $scc
...

---
name:            s_lshr_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_lshr_b64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_LSHR_B64_:%[0-9]+]]:sreg_64 = S_LSHR_B64 [[DEF]], [[COPY]], implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_LSHR_B64 %1:sreg_64, %0, implicit-def $scc
...

---
name:            s_bfe_i64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bfe_i64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64 = S_BFE_I64 [[DEF]], [[COPY]], implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_BFE_I64 %1:sreg_64, %0, implicit-def $scc
...

---
name:            s_bfe_u64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bfe_u64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64 = S_BFE_U64 [[DEF]], [[COPY]], implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_BFE_U64 %1:sreg_64, %0, implicit-def $scc
...

---
name:            s_bfm_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bfm_b64
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_BFM_B64_:%[0-9]+]]:sreg_64 = S_BFM_B64 [[COPY]], 1, implicit-def $scc
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %1:sreg_64 = S_BFM_B64 %0, 1, implicit-def $scc
...

---
name:            s_bitcmp0_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bitcmp0_b64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: $scc = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: S_BITCMP0_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    S_BITCMP0_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
...

---
name:            s_bitcmp1_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bitcmp1_b64
    ; GCN: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GCN-NEXT: $scc = IMPLICIT_DEF
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: S_BITCMP1_B64 [[DEF]], [[COPY]], implicit $scc, implicit-def $scc
    %1:sreg_64 = IMPLICIT_DEF
    $scc = IMPLICIT_DEF
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    S_BITCMP1_B64 %1:sreg_64, %0, implicit $scc, implicit-def $scc
...

---
name:            s_bitreplicate_b64_b32
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bitreplicate_b64_b32
    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: [[S_BITREPLICATE_B64_B32_:%[0-9]+]]:sreg_64 = S_BITREPLICATE_B64_B32 [[COPY]], implicit-def $scc
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    %2:sreg_64 = S_BITREPLICATE_B64_B32 %0, implicit-def $scc
...

---
name:            s_bitset0_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bitset0_b64
    ; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
    ; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
    ; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
    $sgpr0_sgpr1 = IMPLICIT_DEF
    $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
    $sgpr0_sgpr1 = S_BITSET0_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
...

---
name:            s_bitset1_b64
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_bitset1_b64
    ; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
    ; GCN-NEXT: $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
    ; GCN-NEXT: $sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
    $sgpr0_sgpr1 = IMPLICIT_DEF
    $sgpr2 = S_MOV_B32 $src_flat_scratch_base_hi
    $sgpr0_sgpr1 = S_BITSET1_B64 $sgpr2, $sgpr0_sgpr1, implicit-def $scc
...

---
name:            s_ashr_i64_phys_dst
tracksRegLiveness: true
body:             |
  bb.0:

    ; GCN-LABEL: name: s_ashr_i64_phys_dst
    ; GCN: $sgpr0_sgpr1 = IMPLICIT_DEF
    ; GCN-NEXT: $sgpr2 = COPY $src_flat_scratch_base_hi
    ; GCN-NEXT: $sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
    $sgpr0_sgpr1 = IMPLICIT_DEF
    $sgpr2 = COPY $src_flat_scratch_base_hi
    %0:sreg_32 = COPY $src_flat_scratch_base_hi
    $sgpr0_sgpr1 = S_ASHR_I64 $sgpr0_sgpr1, $sgpr2, implicit-def $scc
...