llvm/test/CodeGen/X86/llc-accept-avx10-512.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6

; avx10.x-512 is just avx10.x -- 512 is kept for compatibility purposes.

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.1-512 2>&1 | FileCheck --check-prefixes=CHECK-AVX10_1 %s

; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx10.2-512 2>&1 | FileCheck --check-prefixes=CHECK-AVX10_2 %s

; CHECK-AVX10_1-NOT: is not recognizable
; CHECK-AVX10_2-NOT: is not recognizable

define <32 x bfloat> @foo_avx10.1(<16 x float> %a, <16 x float> %b) {
; CHECK-AVX10_1-LABEL: foo_avx10.1:
; CHECK-AVX10_1:       # %bb.0:
; CHECK-AVX10_1-NEXT:    vcvtne2ps2bf16 %zmm1, %zmm0, %zmm0
; CHECK-AVX10_1-NEXT:    retq
;
; CHECK-AVX10_2-LABEL: foo_avx10.1:
; CHECK-AVX10_2:       # %bb.0:
; CHECK-AVX10_2-NEXT:    vcvtne2ps2bf16 %zmm1, %zmm0, %zmm0
; CHECK-AVX10_2-NEXT:    retq
  %ret = call <32 x bfloat> @llvm.x86.avx512bf16.cvtne2ps2bf16.512(<16 x float> %a, <16 x float> %b)
  ret <32 x bfloat> %ret
}

define <8 x i32> @foo_avx10.2(<8 x double> %f) {
; CHECK-AVX10_1-LABEL: foo_avx10.2:
; CHECK-AVX10_1:       # %bb.0:
; CHECK-AVX10_1-NEXT:    vextractf32x4 $2, %zmm0, %xmm1
; CHECK-AVX10_1-NEXT:    vshufpd {{.*#+}} xmm2 = xmm1[1,0]
; CHECK-AVX10_1-NEXT:    vmovsd {{.*#+}} xmm3 = [-2.147483648E+9,0.0E+0]
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm2, %xmm4
; CHECK-AVX10_1-NEXT:    vmovsd {{.*#+}} xmm5 = [2.147483647E+9,0.0E+0]
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm4, %xmm4
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm4, %ecx
; CHECK-AVX10_1-NEXT:    xorl %eax, %eax
; CHECK-AVX10_1-NEXT:    vucomisd %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm1, %xmm2
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm2, %edx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm1, %xmm1
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %edx
; CHECK-AVX10_1-NEXT:    vmovd %edx, %xmm1
; CHECK-AVX10_1-NEXT:    vpinsrd $1, %ecx, %xmm1, %xmm1
; CHECK-AVX10_1-NEXT:    vextractf32x4 $3, %zmm0, %xmm2
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm2, %xmm4
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm4, %xmm4
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm4, %ecx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vpinsrd $2, %ecx, %xmm1, %xmm1
; CHECK-AVX10_1-NEXT:    vshufpd {{.*#+}} xmm2 = xmm2[1,0]
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm2, %xmm4
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm4, %xmm4
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm4, %ecx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vpinsrd $3, %ecx, %xmm1, %xmm1
; CHECK-AVX10_1-NEXT:    vshufpd {{.*#+}} xmm2 = xmm0[1,0]
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm2, %xmm4
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm4, %xmm4
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm4, %ecx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm0, %xmm2
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm2, %edx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm0, %xmm0
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %edx
; CHECK-AVX10_1-NEXT:    vmovd %edx, %xmm2
; CHECK-AVX10_1-NEXT:    vpinsrd $1, %ecx, %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    vextractf128 $1, %ymm0, %xmm0
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm0, %xmm4
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm4, %xmm4
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm4, %ecx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm0, %xmm0
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vpinsrd $2, %ecx, %xmm2, %xmm2
; CHECK-AVX10_1-NEXT:    vshufpd {{.*#+}} xmm0 = xmm0[1,0]
; CHECK-AVX10_1-NEXT:    vmaxsd %xmm3, %xmm0, %xmm3
; CHECK-AVX10_1-NEXT:    vminsd %xmm5, %xmm3, %xmm3
; CHECK-AVX10_1-NEXT:    vcvttsd2si %xmm3, %ecx
; CHECK-AVX10_1-NEXT:    vucomisd %xmm0, %xmm0
; CHECK-AVX10_1-NEXT:    cmovpl %eax, %ecx
; CHECK-AVX10_1-NEXT:    vpinsrd $3, %ecx, %xmm2, %xmm0
; CHECK-AVX10_1-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
; CHECK-AVX10_1-NEXT:    retq
;
; CHECK-AVX10_2-LABEL: foo_avx10.2:
; CHECK-AVX10_2:       # %bb.0:
; CHECK-AVX10_2-NEXT:    vcvttpd2dqs %zmm0, %ymm0
; CHECK-AVX10_2-NEXT:    retq
  %x = call  <8 x i32> @llvm.fptosi.sat.v8i32.v8f64(<8 x double> %f)
  ret <8 x i32> %x
}