llvm/test/CodeGen/RISCV/opt-w-instrs-p-ext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s

---
name:            merge_sextw_removed
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12

    ; CHECK-LABEL: name: merge_sextw_removed
    ; CHECK: liveins: $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
    ; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[ADDW]], [[ADDW1]], [[ADDW2]]
    ; CHECK-NEXT: $x10 = COPY [[MERGE]]
    ; CHECK-NEXT: PseudoRET
    %0:gpr = COPY $x10
    %1:gpr = COPY $x11
    %2:gpr = COPY $x12
    ; ADDW produces sign-extended results
    %3:gpr = ADDW %0, %1
    %4:gpr = ADDW %1, %2
    %5:gpr = ADDW %0, %2
    %6:gpr = MERGE %3, %4, %5
    %7:gpr = ADDIW %6, 0
    $x10 = COPY %7
    PseudoRET
...
---
name:            mvm_sextw_removed
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12

    ; CHECK-LABEL: name: mvm_sextw_removed
    ; CHECK: liveins: $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
    ; CHECK-NEXT: [[MVM:%[0-9]+]]:gpr = MVM [[ADDW]], [[ADDW1]], [[ADDW2]]
    ; CHECK-NEXT: $x10 = COPY [[MVM]]
    ; CHECK-NEXT: PseudoRET
    %0:gpr = COPY $x10
    %1:gpr = COPY $x11
    %2:gpr = COPY $x12
    %3:gpr = ADDW %0, %1
    %4:gpr = ADDW %1, %2
    %5:gpr = ADDW %0, %2
    %6:gpr = MVM %3, %4, %5
    %7:gpr = ADDIW %6, 0
    $x10 = COPY %7
    PseudoRET
...
---
name:            mvmn_sextw_removed
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12

    ; CHECK-LABEL: name: mvmn_sextw_removed
    ; CHECK: liveins: $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY1]]
    ; CHECK-NEXT: [[ADDW1:%[0-9]+]]:gpr = ADDW [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ADDW2:%[0-9]+]]:gpr = ADDW [[COPY]], [[COPY2]]
    ; CHECK-NEXT: [[MVMN:%[0-9]+]]:gpr = MVMN [[ADDW]], [[ADDW1]], [[ADDW2]]
    ; CHECK-NEXT: $x10 = COPY [[MVMN]]
    ; CHECK-NEXT: PseudoRET
    %0:gpr = COPY $x10
    %1:gpr = COPY $x11
    %2:gpr = COPY $x12
    %3:gpr = ADDW %0, %1
    %4:gpr = ADDW %1, %2
    %5:gpr = ADDW %0, %2
    %6:gpr = MVMN %3, %4, %5
    %7:gpr = ADDIW %6, 0
    $x10 = COPY %7
    PseudoRET
...
---
name:            merge_sextw_not_removed
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x10, $x11, $x12

    ; CHECK-LABEL: name: merge_sextw_not_removed
    ; CHECK: liveins: $x10, $x11, $x12
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
    ; CHECK-NEXT: [[MERGE:%[0-9]+]]:gpr = MERGE [[COPY]], [[COPY1]], [[COPY2]]
    ; CHECK-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[MERGE]], 0
    ; CHECK-NEXT: $x10 = COPY [[ADDIW]]
    ; CHECK-NEXT: PseudoRET
    %0:gpr = COPY $x10
    %1:gpr = COPY $x11
    %2:gpr = COPY $x12
    %3:gpr = MERGE %0, %1, %2
    %4:gpr = ADDIW %3, 0
    $x10 = COPY %4
    PseudoRET
...