llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier-fastregalloc.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -stop-after=postrapseudos -o - < %s | FileCheck -enable-var-scope -check-prefix=MIR %s


define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
  ; MIR-LABEL: name: gws_barrier_offset0
  ; MIR: bb.0 (%ir-block.0):
  ; MIR-NEXT:   liveins: $sgpr8_sgpr9
  ; MIR-NEXT: {{  $}}
  ; MIR-NEXT:   renamable $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s32) from %ir.val.kernarg.offset, align 16, addrspace 4)
  ; MIR-NEXT:   $m0 = S_MOV_B32 0
  ; MIR-NEXT:   $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec
  ; MIR-NEXT:   BUNDLE implicit killed renamable $vgpr0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource") {
  ; MIR-NEXT:     DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource")
  ; MIR-NEXT:     S_WAITCNT 0
  ; MIR-NEXT:   }
  ; MIR-NEXT:   S_ENDPGM 0
  call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
  ret void
}


declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #1

attributes #0 = { nounwind }
attributes #1 = { convergent inaccessiblememonly nounwind }