| # RUN: llvm-mc -triple=xtensa -mattr=+debug,+density -disassemble %s | FileCheck -check-prefixes=CHECK-DEBUG %s |
| # RUN: not llvm-mc -triple=xtensa -disassemble %s 2>&1 | FileCheck --implicit-check-not=warning: -check-prefixes=CHECK-CORE %s |
| |
| ## Verify that binary code is correctly disassembled with |
| ## Xtensa debug option enabled. Also verify that dissasembling without |
| ## Xtensa debug option generates warnings. |
| |
| [0x10,0x41,0x00] |
| # CHECK-DEBUG: break 1, 1 |
| # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x2d,0xf1] |
| # CHECK-DEBUG: break.n 1 |
| # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0xe0,0x73,0x00] |
| # CHECK-DEBUG: lddr32.p a3 |
| # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0xf0,0x73,0x00] |
| # CHECK-DEBUG: sddr32.p a3 |
| # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0xec, 0x61] |
| #CHECK-DEBUG: xsr a2, icount |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0xed, 0x61] |
| #CHECK-DEBUG: xsr a2, icountlevel |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x60, 0x61] |
| #CHECK-DEBUG: xsr a2, ibreakenable |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x68, 0x61] |
| #CHECK-DEBUG: xsr a2, ddr |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x80, 0x61] |
| #CHECK-DEBUG: xsr a2, ibreaka0 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x81, 0x61] |
| #CHECK-DEBUG: xsr a2, ibreaka1 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x90, 0x61] |
| #CHECK-DEBUG: xsr a2, dbreaka0 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0x91, 0x61] |
| #CHECK-DEBUG: xsr a2, dbreaka1 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0xa0, 0x61] |
| #CHECK-DEBUG: xsr a2, dbreakc0 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
| |
| [0x20, 0xa1, 0x61] |
| #CHECK-DEBUG: xsr a2, dbreakc1 |
| #CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding |
