llvm/test/CodeGen/RISCV/GlobalISel/fpr-gpr-copy-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv64 -global-isel -mattr=+d -target-abi=lp64 \
; RUN:   -verify-machineinstrs < %s | FileCheck -check-prefix=RV64I %s

; Test copying between FPR64 and GPR on RV64.
; FIXME: This test should be replaced with a more general calling convention
; test once we have more FP implemented.

define double @fadd_f64(double %x, double %y) {
; RV64I-LABEL: fadd_f64:
; RV64I:       # %bb.0:
; RV64I-NEXT:    fmv.d.x fa5, a0
; RV64I-NEXT:    fmv.d.x fa4, a1
; RV64I-NEXT:    fadd.d fa5, fa5, fa4
; RV64I-NEXT:    fmv.x.d a0, fa5
; RV64I-NEXT:    ret
  %a = fadd double %x, %y
  ret double %a
}

; Test copying between FPR32 and GPR on RV64.
; FIXME: This test should be replaced with a more general calling convention
; test once we have more FP implemented.

define float @fadd_f32(float %x, float %y) {
; RV32I-LABEL: fadd:
; RV32I:       # %bb.0:
; RV32I-NEXT:    fmv.d.x fa5, a0
; RV32I-NEXT:    fmv.d.x fa4, a1
; RV32I-NEXT:    fadd.d fa5, fa5, fa4
; RV32I-NEXT:    fmv.x.d a0, fa5
; RV32I-NEXT:    ret
; RV64I-LABEL: fadd_f32:
; RV64I:       # %bb.0:
; RV64I-NEXT:    fmv.w.x fa5, a0
; RV64I-NEXT:    fmv.w.x fa4, a1
; RV64I-NEXT:    fadd.s fa5, fa5, fa4
; RV64I-NEXT:    fmv.x.w a0, fa5
; RV64I-NEXT:    ret
  %a = fadd float %x, %y
  ret float %a
}