llvm/test/CodeGen/AMDGPU/abs_i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s
; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=R600 %s

define amdgpu_kernel void @abs_v1(ptr addrspace(1) %out, i32 %arg) {
; GFX9-LABEL: abs_v1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x8
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_abs_i32 s2, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-NEXT:    s_endpgm
;
; R600-LABEL: abs_v1:
; R600:       ; %bb.0:
; R600-NEXT:    ALU 4, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT:    CF_END
; R600-NEXT:    PAD
; R600-NEXT:    ALU clause starting at 4:
; R600-NEXT:     MOV * T0.W, KC0[2].Z,
; R600-NEXT:     SUB_INT * T1.W, 0.0, PV.W,
; R600-NEXT:     MAX_INT T0.X, T0.W, PV.W,
; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)
  store i32 %res, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @abs_v2(ptr addrspace(1) %out, i32 %arg) {
; GFX9-LABEL: abs_v2:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x8
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_abs_i32 s2, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-NEXT:    s_endpgm
;
; R600-LABEL: abs_v2:
; R600:       ; %bb.0:
; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT:    CF_END
; R600-NEXT:    PAD
; R600-NEXT:    ALU clause starting at 4:
; R600-NEXT:     SUB_INT * T0.W, 0.0, KC0[2].Z,
; R600-NEXT:     MAX_INT T0.X, KC0[2].Z, PV.W,
; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %neg = sub i32 0, %arg
  %cond = icmp sgt i32 %arg, %neg
  %res = select i1 %cond, i32 %arg, i32 %neg
  store i32 %res, ptr addrspace(1) %out, align 4
  ret void
}

define amdgpu_kernel void @abs_v3(ptr addrspace(1) %out, i32 %arg) {
; GFX9-LABEL: abs_v3:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dword s2, s[4:5], 0x8
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    s_abs_i32 s2, s2
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-NEXT:    s_endpgm
;
; R600-LABEL: abs_v3:
; R600:       ; %bb.0:
; R600-NEXT:    ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT:    MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT:    CF_END
; R600-NEXT:    PAD
; R600-NEXT:    ALU clause starting at 4:
; R600-NEXT:     SUB_INT * T0.W, 0.0, KC0[2].Z,
; R600-NEXT:     MAX_INT T0.X, PV.W, KC0[2].Z,
; R600-NEXT:     LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT:    2(2.802597e-45), 0(0.000000e+00)
  %neg = sub i32 0, %arg
  %cond = icmp sgt i32 %neg, %arg
  %res = select i1 %cond, i32 %neg, i32 %arg
  store i32 %res, ptr addrspace(1) %out, align 4
  ret void
}