llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s

---
name: sext_inreg_s_s32_1
legalized: true

body: |
  bb.0:
    liveins: $sgpr0

    ; CHECK-LABEL: name: sext_inreg_s_s32_1
    ; CHECK: liveins: $sgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:sgpr(s32) = G_SEXT_INREG [[COPY]], 1
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_SEXT_INREG %0, 1
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_s_s64_1
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: sext_inreg_s_s64_1
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 1
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s64) = G_SEXT_INREG %0, 1
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_s_s64_31
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: sext_inreg_s_s64_31
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 31
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s64) = G_SEXT_INREG %0, 31
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_s_s64_32
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: sext_inreg_s_s64_32
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 32
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s64) = G_SEXT_INREG %0, 32
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_s_s64_33
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1

    ; CHECK-LABEL: name: sext_inreg_s_s64_33
    ; CHECK: liveins: $sgpr0_sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:sgpr(s64) = G_SEXT_INREG [[COPY]], 32
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s64)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s64) = G_SEXT_INREG %0, 32
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s32_1
legalized: true

body: |
  bb.0:
    liveins: $vgpr0

    ; CHECK-LABEL: name: sext_inreg_v_s32_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[COPY]], 1
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[SEXT_INREG]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_SEXT_INREG %0, 1
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_1
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_1
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:vgpr(s32) = G_FREEZE [[UV]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[FREEZE]], 1
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 1
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_31
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_31
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:vgpr(s32) = G_FREEZE [[UV]]
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[FREEZE]], 31
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[SEXT_INREG]], [[C]](s32)
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SEXT_INREG]](s32), [[ASHR]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 31
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_32
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:vgpr(s32) = G_FREEZE [[UV]]
    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31
    ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s32) = G_ASHR [[FREEZE]], [[C]](s32)
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[FREEZE]](s32), [[ASHR]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 32
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_33
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_33
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV1]], 1
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[SEXT_INREG]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 33
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_35
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_35
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV1]], 3
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[SEXT_INREG]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 35
    S_ENDPGM 0, implicit %1

...

---
name: sext_inreg_v_s64_63
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1

    ; CHECK-LABEL: name: sext_inreg_v_s64_63
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:vgpr(s32) = G_SEXT_INREG [[UV1]], 31
    ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[SEXT_INREG]](s32)
    ; CHECK-NEXT: S_ENDPGM 0, implicit [[MV]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_SEXT_INREG %0, 63
    S_ENDPGM 0, implicit %1

...