llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-sext-inreg.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s

---
name: inreg8_inreg16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: inreg8_inreg16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 8
    ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
    %copy:_(s32) = COPY $vgpr0
    %inreg:_(s32) = G_SEXT_INREG %copy, 8
    %inreg1:_(s32) = G_SEXT_INREG %inreg, 16
    $vgpr0 = COPY %inreg1
...

---
name: inreg16_inreg16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: inreg16_inreg16
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 16
    ; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
    %copy:_(s32) = COPY $vgpr0
    %inreg:_(s32) = G_SEXT_INREG %copy, 16
    %inreg1:_(s32) = G_SEXT_INREG %inreg, 16
    $vgpr0 = COPY %inreg1
...

---
name: inreg16_inreg8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: inreg16_inreg8
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
    ; CHECK-NEXT: %inreg1:_(s32) = G_SEXT_INREG %copy, 8
    ; CHECK-NEXT: $vgpr0 = COPY %inreg1(s32)
    %copy:_(s32) = COPY $vgpr0
    %inreg:_(s32) = G_SEXT_INREG %copy, 16
    %inreg1:_(s32) = G_SEXT_INREG %inreg, 8
    $vgpr0 = COPY %inreg1
...

---
name: inreg16_inreg32_64bit
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: inreg16_inreg32_64bit
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 16
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)
    %copy:_(s64) = COPY $vgpr0_vgpr1
    %inreg:_(s64) = G_SEXT_INREG %copy, 16
    %inreg1:_(s64) = G_SEXT_INREG %inreg, 32
    $vgpr0_vgpr1 = COPY %inreg1
...

---
name: inreg32_inreg32_64bit
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: inreg32_inreg32_64bit
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 32
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)
    %copy:_(s64) = COPY $vgpr0_vgpr1
    %inreg:_(s64) = G_SEXT_INREG %copy, 32
    %inreg1:_(s64) = G_SEXT_INREG %inreg, 32
    $vgpr0_vgpr1 = COPY %inreg1
...

---
name: inreg32_inreg16_64bit
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: inreg32_inreg16_64bit
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: %inreg1:_(s64) = G_SEXT_INREG %copy, 16
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg1(s64)
    %copy:_(s64) = COPY $vgpr0_vgpr1
    %inreg:_(s64) = G_SEXT_INREG %copy, 32
    %inreg1:_(s64) = G_SEXT_INREG %inreg, 16
    $vgpr0_vgpr1 = COPY %inreg1
...

---
name: vector_inreg8_inreg16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-LABEL: name: vector_inreg8_inreg16
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)
    %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8
    %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
...

---
name: vector_inreg16_inreg16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-LABEL: name: vector_inreg16_inreg16
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)
    %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
    %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
...

---
name: vector_inreg16_inreg8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-LABEL: name: vector_inreg16_inreg8
    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    ; CHECK-NEXT: %inreg1:_(<4 x s32>) = G_SEXT_INREG %copy, 8
    ; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1(<4 x s32>)
    %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
    %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
    %inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 8
    $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
...