llvm/test/CodeGen/AArch64/sve-ptest-removal-cmpeq.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s

# Test instruction sequences where PTEST is redundant and thus gets removed.
---
name:            cmpeq_nxv16i8
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv16i8
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[COPY2]], [[COPY1]], [[COPY]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, killed %3, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_nxv8i16
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
  - { id: 7, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv8i16
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_PPzZZ_H [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY2]], [[CMPEQ_PPzZZ_H]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %4:ppr = CMPEQ_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, %4, implicit-def $nzcv
    %6:gpr32 = COPY $wzr
    %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
    $w0 = COPY %7
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_nxv4i32
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
  - { id: 7, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv4i32
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_S:%[0-9]+]]:ppr = CMPEQ_PPzZZ_S [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY2]], [[CMPEQ_PPzZZ_S]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %4:ppr = CMPEQ_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, %4, implicit-def $nzcv
    %6:gpr32 = COPY $wzr
    %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
    $w0 = COPY %7
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_nxv2i64
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
  - { id: 7, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv2i64
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_D:%[0-9]+]]:ppr = CMPEQ_PPzZZ_D [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY2]], [[CMPEQ_PPzZZ_D]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %4:ppr = CMPEQ_PPzZZ_D %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, %4, implicit-def $nzcv
    %6:gpr32 = COPY $wzr
    %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
    $w0 = COPY %7
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv16i8
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv16i8
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_B:%[0-9]+]]:ppr = CMPEQ_PPzZI_B [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: PTEST_PP killed [[PTRUE_B]], killed [[CMPEQ_PPzZI_B]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
    %3:ppr = PTRUE_B 31, implicit $vg
    PTEST_PP killed %3, killed %2, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv8i16
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: ppr }
  - { id: 5, class: gpr32 }
  - { id: 6, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv8i16
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_H:%[0-9]+]]:ppr = CMPEQ_PPzZI_H [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY1]], [[CMPEQ_PPzZI_H]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_H %0, %1, 0, implicit-def dead $nzcv
    PTEST_PP %0, %2, implicit-def $nzcv
    %5:gpr32 = COPY $wzr
    %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
    $w0 = COPY %6
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv4i32
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: ppr }
  - { id: 5, class: gpr32 }
  - { id: 6, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv4i32
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_S:%[0-9]+]]:ppr = CMPEQ_PPzZI_S [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY1]], [[CMPEQ_PPzZI_S]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_S %0, %1, 0, implicit-def dead $nzcv
    PTEST_PP %0, %2, implicit-def $nzcv
    %5:gpr32 = COPY $wzr
    %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
    $w0 = COPY %6
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv2i64
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: ppr }
  - { id: 5, class: gpr32 }
  - { id: 6, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv2i64
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_D:%[0-9]+]]:ppr = CMPEQ_PPzZI_D [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY1]], [[CMPEQ_PPzZI_D]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_D %0, %1, 0, implicit-def dead $nzcv
    PTEST_PP %0, %2, implicit-def $nzcv
    %5:gpr32 = COPY $wzr
    %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
    $w0 = COPY %6
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_wide_nxv16i8
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_wide_nxv16i8
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_WIDE_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_WIDE_PPzZZ_B [[COPY2]], [[COPY1]], [[COPY]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %3:ppr = CMPEQ_WIDE_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, killed %3, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_wide_nxv8i16
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
  - { id: 7, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_wide_nxv8i16
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_WIDE_PPzZZ_H:%[0-9]+]]:ppr = CMPEQ_WIDE_PPzZZ_H [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY2]], [[CMPEQ_WIDE_PPzZZ_H]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %4:ppr = CMPEQ_WIDE_PPzZZ_H %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, %4, implicit-def $nzcv
    %6:gpr32 = COPY $wzr
    %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
    $w0 = COPY %7
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_wide_nxv4i32
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: ppr }
  - { id: 6, class: gpr32 }
  - { id: 7, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_wide_nxv4i32
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_WIDE_PPzZZ_S:%[0-9]+]]:ppr = CMPEQ_WIDE_PPzZZ_S [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[COPY2]], [[CMPEQ_WIDE_PPzZZ_S]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %4:ppr = CMPEQ_WIDE_PPzZZ_S %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, %4, implicit-def $nzcv
    %6:gpr32 = COPY $wzr
    %7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
    $w0 = COPY %7
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv16i8_ptest_not_all_active
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_not_all_active
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_B:%[0-9]+]]:ppr = CMPEQ_PPzZI_B [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 0, implicit $vg
    ; CHECK-NEXT: PTEST_PP killed [[PTRUE_B]], killed [[CMPEQ_PPzZI_B]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
    %3:ppr = PTRUE_B 0, implicit $vg
    PTEST_PP killed %3, killed %2, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv16i8_ptest_of_halfs
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_of_halfs
    ; CHECK: liveins: $p0, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_B:%[0-9]+]]:ppr = CMPEQ_PPzZI_B [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr = PTRUE_H 31, implicit $vg
    ; CHECK-NEXT: PTEST_PP killed [[PTRUE_H]], killed [[CMPEQ_PPzZI_B]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
    %3:ppr = PTRUE_H 31, implicit $vg
    PTEST_PP killed %3, killed %2, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_imm_nxv16i8_ptest_with_unique_pg
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: ppr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$p1', virtual-reg: '%3' }
  - { reg: '$z0', virtual-reg: '%1' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $p1, $z0

    ; CHECK-LABEL: name: cmpeq_imm_nxv16i8_ptest_with_unique_pg
    ; CHECK: liveins: $p0, $p1, $z0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZI_B:%[0-9]+]]:ppr = CMPEQ_PPzZI_B [[COPY1]], [[COPY]], 0, implicit-def dead $nzcv
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr = COPY $p1
    ; CHECK-NEXT: PTEST_PP killed [[COPY2]], killed [[CMPEQ_PPzZI_B]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %2:ppr = CMPEQ_PPzZI_B %0, %1, 0, implicit-def dead $nzcv
    %3:ppr = COPY $p1
    PTEST_PP killed %3, killed %2, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_nxv16i8_ptest_with_matching_operands
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr_3b }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr }
  - { id: 4, class: gpr32 }
  - { id: 5, class: gpr32 }
liveins:
  - { reg: '$p0', virtual-reg: '%0' }
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $p0, $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv16i8_ptest_with_matching_operands
    ; CHECK: liveins: $p0, $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY $p0
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[COPY2]], [[COPY1]], [[COPY]], implicit-def dead $nzcv
    ; CHECK-NEXT: PTEST_PP [[CMPEQ_PPzZZ_B]], killed [[CMPEQ_PPzZZ_B]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %2:zpr = COPY $z1
    %1:zpr = COPY $z0
    %0:ppr_3b = COPY $p0
    %3:ppr = CMPEQ_PPzZZ_B %0, %1, %2, implicit-def dead $nzcv
    PTEST_PP %3, killed %3, implicit-def $nzcv
    %4:gpr32 = COPY $wzr
    %5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
    $w0 = COPY %5
    RET_ReallyLR implicit $w0

...
---
name:            cmpeq_nxv16i8_ptest_with_register_class_mismatch
alignment:       2
tracksRegLiveness: true
registers:
  - { id: 0, class: ppr }
  - { id: 1, class: zpr }
  - { id: 2, class: zpr }
  - { id: 3, class: ppr_3b }
  - { id: 4, class: ppr }
  - { id: 5, class: gpr32 }
  - { id: 6, class: gpr32 }
liveins:
  - { reg: '$z0', virtual-reg: '%1' }
  - { reg: '$z1', virtual-reg: '%2' }
frameInfo:
  maxCallFrameSize: 0
body:             |
  bb.0:
    liveins: $z0, $z1

    ; CHECK-LABEL: name: cmpeq_nxv16i8_ptest_with_register_class_mismatch
    ; CHECK: liveins: $z0, $z1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:zpr = COPY $z0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z1
    ; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ppr_3b = COPY [[PTRUE_B]]
    ; CHECK-NEXT: [[CMPEQ_PPzZZ_B:%[0-9]+]]:ppr = CMPEQ_PPzZZ_B [[COPY2]], [[COPY]], [[COPY1]], implicit-def $nzcv
    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY3]], $wzr, 0, implicit $nzcv
    ; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
    ; CHECK-NEXT: RET_ReallyLR implicit $w0
    %1:zpr = COPY $z0
    %2:zpr = COPY $z1
    %0:ppr = PTRUE_B 31, implicit $vg
    %3:ppr_3b = COPY %0
    %4:ppr = CMPEQ_PPzZZ_B %3, %1, %2, implicit-def dead $nzcv
    PTEST_PP %0, killed %4, implicit-def $nzcv
    %5:gpr32 = COPY $wzr
    %6:gpr32 = CSINCWr %5, $wzr, 0, implicit $nzcv
    $w0 = COPY %6
    RET_ReallyLR implicit $w0

...