llvm/test/CodeGen/AArch64/ldst-implicitop.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=aarch64-- -run-pass=aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
# Check that we copy implicit operands.
---
name:            impdef_op1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $lr
    ; CHECK-LABEL: name: impdef_op1
    ; CHECK: liveins: $lr
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $q5, renamable $q20 = LDPQi renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
    ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
    ; CHECK-NEXT: RET_ReallyLR
    renamable $q5 = LDRQui renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    renamable $q20 = LDRQui renamable $lr, 4 :: (load (s128))
    $q0 = ORRv16i8 $q4, killed $q4
    $q1 = ORRv16i8 $q5, killed $q5
    RET_ReallyLR
...
---
name:            impdef_op2
body:             |
  bb.0:
    liveins: $lr
    ; CHECK-LABEL: name: impdef_op2
    ; CHECK: liveins: $lr
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $q20, renamable $q5 = LDPQi renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
    ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
    ; CHECK-NEXT: RET_ReallyLR
    renamable $q20 = LDRQui renamable $lr, 3 :: (load (s128))
    renamable $q5 = LDRQui renamable $lr, 4, implicit-def $q4_q5 :: (load (s128))
    $q0 = ORRv16i8 $q4, killed $q4
    $q1 = ORRv16i8 $q5, killed $q5
    RET_ReallyLR
...
---
name:            impdef_both
body:             |
  bb.0:
    liveins: $lr
    ; CHECK-LABEL: name: impdef_both
    ; CHECK: liveins: $lr
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $q5, renamable $q20 = LDPQi renamable $lr, 3, implicit-def $q4_q5, implicit-def $q20_q21 :: (load (s128))
    ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
    ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
    ; CHECK-NEXT: $q2 = ORRv16i8 $q20, killed $q20
    ; CHECK-NEXT: $q3 = ORRv16i8 $q21, killed $q21
    ; CHECK-NEXT: RET_ReallyLR
    renamable $q5 = LDRQui renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    renamable $q20 = LDRQui renamable $lr, 4, implicit-def $q20_q21 :: (load (s128))
    $q0 = ORRv16i8 $q4, killed $q4
    $q1 = ORRv16i8 $q5, killed $q5
    $q2 = ORRv16i8 $q20, killed $q20
    $q3 = ORRv16i8 $q21, killed $q21
    RET_ReallyLR
...
---
name:            impdef_both_same
body:             |
  bb.0:
    liveins: $lr
    ; CHECK-LABEL: name: impdef_both_same
    ; CHECK: liveins: $lr
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $q5, renamable $q20 = LDPQi renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    ; CHECK-NEXT: $q0 = ORRv16i8 $q4, killed $q4
    ; CHECK-NEXT: $q1 = ORRv16i8 $q5, killed $q5
    ; CHECK-NEXT: RET_ReallyLR
    renamable $q5 = LDRQui renamable $lr, 3, implicit-def $q4_q5 :: (load (s128))
    renamable $q20 = LDRQui renamable $lr, 4, implicit-def $q4_q5 :: (load (s128))
    $q0 = ORRv16i8 $q4, killed $q4
    $q1 = ORRv16i8 $q5, killed $q5
    RET_ReallyLR
...