llvm/test/CodeGen/AArch64/arm64-cvt-simd-fptoi.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-NOFPRCVT
; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK
; RUN: llc < %s -mtriple aarch64-unknown-unknown -global-isel -global-isel-abort=2 -mattr=+fprcvt,+fullfp16 2>&1  | FileCheck %s --check-prefixes=CHECK

; CHECK-GI: warning: Instruction selection used fallback path for fptosi_i32_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i64_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptosi_i32_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f16_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f32_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i64_f64_simd
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fptoui_i32_f32_simd

;
; FPTOI
;

define float @test_fptosi_f16_i32_simd(half %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f16_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, h0
; CHECK-NEXT:    ret
  %r = fptosi half %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}

define double @test_fptosi_f16_i64_simd(half %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f16_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f16_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, h0
; CHECK-NEXT:    ret
  %r = fptosi half %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}

define float @test_fptosi_f64_i32_simd(double %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f64_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, d0
; CHECK-NEXT:    ret
  %r = fptosi double %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}

define double @test_fptosi_f32_i64_simd(float %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f32_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    ret
  %r = fptosi float %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}

define double @test_fptosi_f64_i64_simd(double %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f64_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f64_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %r = fptosi double %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}


define float @test_fptosi_f32_i32_simd(float %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptosi_f32_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptosi_f32_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %r = fptosi float %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}

define float @test_fptoui_f16_i32_simd(half %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f16_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, h0
; CHECK-NEXT:    ret
  %r = fptoui half %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}

define double @test_fptoui_f16_i64_simd(half %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f16_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f16_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, h0
; CHECK-NEXT:    ret
  %r = fptoui half %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}

define float @test_fptoui_f64_i32_simd(double %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f64_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, d0
; CHECK-NEXT:    ret
  %r = fptoui double %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}

define double @test_fptoui_f32_i64_simd(float %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f32_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, s0
; CHECK-NEXT:    ret
  %r = fptoui float %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}

define double @test_fptoui_f64_i64_simd(double %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f64_i64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f64_i64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0
; CHECK-NEXT:    ret
  %r = fptoui double %a to i64
  %bc = bitcast i64 %r to double
  ret double %bc
}


define float @test_fptoui_f32_i32_simd(float %a)  {
; CHECK-NOFPRCVT-LABEL: test_fptoui_f32_i32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: test_fptoui_f32_i32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0
; CHECK-NEXT:    ret
  %r = fptoui float %a to i32
  %bc = bitcast i32 %r to float
  ret float %bc
}


;
; FPTOI strictfp
;

define float @fptosi_i32_f16_simd(half %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f16_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i32_f16_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, h0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i32 %val to float
  ret float %sum
}

define double @fptosi_i64_f16_simd(half %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f16_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i64_f16_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, h0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i64 %val to double
  ret double %sum
}

define double @fptosi_i64_f32_simd(float %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i64_f32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptosi.i64.f32(float %x, metadata !"fpexcept.strict")
  %bc = bitcast i64 %val to double
  ret double %bc
}

define float @fptosi_i32_f64_simd(double %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i32_f64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, d0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %x, metadata !"fpexcept.strict")
  %bc = bitcast i32 %val to float
  ret float %bc
}

define double @fptosi_i64_f64_simd(double %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i64_f64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i64_f64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptosi.i64.f64(double %x, metadata !"fpexcept.strict")
  %bc = bitcast i64 %val to double
  ret double %bc
}

define float @fptosi_i32_f32_simd(float %x)  {
; CHECK-NOFPRCVT-LABEL: fptosi_i32_f32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptosi_i32_f32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %x, metadata !"fpexcept.strict")
  %bc = bitcast i32 %val to float
  ret float %bc
}



define float @fptoui_i32_f16_simd(half %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f16_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i32_f16_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, h0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i32 %val to float
  ret float %sum
}

define double @fptoui_i64_f16_simd(half %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f16_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i64_f16_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, h0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %x, metadata !"fpexcept.strict")
  %sum = bitcast i64 %val to double
  ret double %sum
}

define double @fptoui_i64_f32_simd(float %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i64_f32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, s0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptoui.i64.f32(float %x, metadata !"fpexcept.strict")
  %bc = bitcast i64 %val to double
  ret double %bc
}

define float @fptoui_i32_f64_simd(double %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i32_f64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, d0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %x, metadata !"fpexcept.strict")
  %bc = bitcast i32 %val to float
  ret float %bc
}

define double @fptoui_i64_f64_simd(double %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i64_f64_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i64_f64_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0
; CHECK-NEXT:    ret
  %val = call i64 @llvm.experimental.constrained.fptoui.i64.f64(double %x, metadata !"fpexcept.strict")
  %bc = bitcast i64 %val to double
  ret double %bc
}

define float @fptoui_i32_f32_simd(float %x)  {
; CHECK-NOFPRCVT-LABEL: fptoui_i32_f32_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fptoui_i32_f32_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0
; CHECK-NEXT:    ret
  %val = call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %x, metadata !"fpexcept.strict")
  %bc = bitcast i32 %val to float
  ret float %bc
}

;
; FPTOI rounding
;


define double @fcvtas_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = fptosi float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtas_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = fptosi double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtas_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtas_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


define double @fcvtau_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = fptoui float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtau_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = fptoui double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtau_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtau_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


define double @fcvtms_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = fptosi float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtms_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = fptosi double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtms_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtms_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}



define double @fcvtmu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = fptoui float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtmu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = fptoui double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtmu_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtmu_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


define double @fcvtps_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = fptosi float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtps_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = fptosi double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtps_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtps_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


define double @fcvtpu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = fptoui float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtpu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = fptoui double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtpu_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtpu_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


define double @fcvtzs_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = fptosi float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzs_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = fptosi double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzs_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzs_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtzu_ds_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ds_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = fptoui float %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzu_sd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_sd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = fptoui double %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzu_ss_round_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ss_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = fptosi float %r to i32
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzu_dd_round_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_round_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_dd_round_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = fptosi double %r to i64
  %bc = bitcast i64 %i to double
  ret double %bc
}


;
; FPTOI saturating
;

define float @fcvtzs_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_sh_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, h0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptosi.sat.i32.f16(half %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzs_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_dh_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, h0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptosi.sat.i64.f16(half %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtzs_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ds_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptosi.sat.i64.f32(float %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzs_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_sd_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, d0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptosi.sat.i32.f64(double %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzs_ss_sat_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ss_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzs_dd_sat_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_dd_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzu_sh_sat_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_sh_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, h0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzu_dh_sat_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_dh_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, h0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtzu_ds_sat_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ds_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, s0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzu_sd_sat_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_sd_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, d0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzu_ss_sat_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ss_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %a)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzu_dd_sat_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_sat_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_dd_sat_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %a)
  %bc = bitcast i64 %i to double
  ret double %bc
}

;
; FPTOI saturating with rounding
;

define float @fcvtas_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.round.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtas_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.round.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtas_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtas_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtas_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtas_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtas_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtas_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtau_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.round.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtau_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.round.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtau_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtau_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtau w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtau s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtau_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.round.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtau_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtau_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtas d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtau_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtas d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.round.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtms_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.floor.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtms_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.floor.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtms_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtms_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtms_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtms_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtms_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtms_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtmu_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.floor.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtmu_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.floor.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtmu_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtmu_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtmu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtmu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtmu_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.floor.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtmu_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtmu_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtms d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtmu_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtms d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.floor.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtps_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtps_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtps_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtps_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtps_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtps_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtps_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtps_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtpu_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtpu_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtpu_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtpu_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtpu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtpu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtpu_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.ceil.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtpu_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtpu_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtps d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtpu_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtps d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.ceil.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzs_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzs_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtzs_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzs_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzs_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzs_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzs_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzs d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzs_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzs d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzu_sh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_sh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, h0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_sh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzu_dh_simd(half %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_dh_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, h0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_dh_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, h0
; CHECK-NEXT:    ret
  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define double @fcvtzu_ds_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ds_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu x8, s0
; CHECK-NOFPRCVT-NEXT:    fmov d0, x8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ds_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}

define float @fcvtzu_sd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_sd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu w8, d0
; CHECK-NOFPRCVT-NEXT:    fmov s0, w8
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_sd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define float @fcvtzu_ss_simd(float %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_ss_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu s0, s0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_ss_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu s0, s0
; CHECK-NEXT:    ret
  %r = call float @llvm.trunc.f32(float %a)
  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
  %bc = bitcast i32 %i to float
  ret float %bc
}

define double @fcvtzu_dd_simd(double %a) {
; CHECK-NOFPRCVT-LABEL: fcvtzu_dd_simd:
; CHECK-NOFPRCVT:       // %bb.0:
; CHECK-NOFPRCVT-NEXT:    fcvtzu d0, d0
; CHECK-NOFPRCVT-NEXT:    ret
;
; CHECK-LABEL: fcvtzu_dd_simd:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fcvtzu d0, d0
; CHECK-NEXT:    ret
  %r = call double @llvm.trunc.f64(double %a)
  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
  %bc = bitcast i64 %i to double
  ret double %bc
}