llvm/test/CodeGen/AArch64/GlobalISel/select-scalar-merge.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"

  define void @gmerge_s64_s32() { ret void }
...

---
name:            gmerge_s64_s32
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.0:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: gmerge_s64_s32
    ; CHECK: liveins: $w0, $w1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY $w1
    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
    ; CHECK-NEXT: [[SUBREG_TO_REG1:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
    ; CHECK-NEXT: [[BFMXri:%[0-9]+]]:gpr64 = BFMXri [[SUBREG_TO_REG]], [[SUBREG_TO_REG1]], 32, 31
    ; CHECK-NEXT: $x0 = COPY [[BFMXri]]
    %0(s32) = COPY $w0
    %1(s32) = COPY $w1
    %2(s64) = G_MERGE_VALUES %0(s32), %1(s32)
    $x0 = COPY %2(s64)
...