llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1200 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX1200 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=0 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -global-isel=1 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s

define amdgpu_kernel void @workgroup_id_x(ptr addrspace(1) %ptrx) {
;
; GFX9-LABEL: workgroup_id_x:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX9-NEXT:    v_mov_b32_e32 v0, ttmp9
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
; GFX9-NEXT:    s_endpgm
;
; GFX1200-LABEL: workgroup_id_x:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX1200-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1200-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: workgroup_id_x:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-SDAG-NEXT:    s_bfe_u32 s2, ttmp6, 0x4000c
; GFX1250-SDAG-NEXT:    s_and_b32 s3, ttmp6, 15
; GFX1250-SDAG-NEXT:    s_add_co_i32 s2, s2, 1
; GFX1250-SDAG-NEXT:    s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT:    s_getreg_b32 s4, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-SDAG-NEXT:    s_mul_i32 s2, ttmp9, s2
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT:    s_add_co_i32 s3, s3, s2
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s4, 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s2, ttmp9, s3
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: workgroup_id_x:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX1250-GISEL-NEXT:    s_bfe_u32 s2, ttmp6, 0x4000c
; GFX1250-GISEL-NEXT:    s_and_b32 s3, ttmp6, 15
; GFX1250-GISEL-NEXT:    s_add_co_i32 s2, s2, 1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    s_getreg_b32 s4, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-GISEL-NEXT:    s_mul_i32 s2, ttmp9, s2
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-GISEL-NEXT:    s_add_co_i32 s3, s3, s2
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s4, 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s2, ttmp9, s3
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    s_endpgm
; GFX12-LABEL: workgroup_id_x:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b64 s[0:1], s[4:5], 0x0
; GFX12-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT:    s_endpgm
  %idx = call i32 @llvm.amdgcn.workgroup.id.x()
  store i32 %idx, ptr addrspace(1) %ptrx

  ret void
}

define amdgpu_kernel void @workgroup_id_xy(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry) {
; GFX9-LABEL: workgroup_id_xy:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT:    v_mov_b32_e32 v0, ttmp9
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_and_b32 s4, ttmp7, 0xffff
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
; GFX9-NEXT:    global_store_dword v1, v2, s[2:3]
; GFX9-NEXT:    s_endpgm
;
; GFX1200-LABEL: workgroup_id_xy:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1200-NEXT:    s_and_b32 s4, ttmp7, 0xffff
; GFX1200-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX1200-NEXT:    v_mov_b32_e32 v2, s4
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    s_clause 0x1
; GFX1200-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1200-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX1200-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: workgroup_id_xy:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-SDAG-NEXT:    s_bfe_u32 s6, ttmp6, 0x40010
; GFX1250-SDAG-NEXT:    s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT:    s_and_b32 s4, ttmp7, 0xffff
; GFX1250-SDAG-NEXT:    s_add_co_i32 s6, s6, 1
; GFX1250-SDAG-NEXT:    s_bfe_u32 s7, ttmp6, 0x4000c
; GFX1250-SDAG-NEXT:    s_mul_i32 s5, s4, s6
; GFX1250-SDAG-NEXT:    s_bfe_u32 s6, ttmp6, 0x40004
; GFX1250-SDAG-NEXT:    s_add_co_i32 s7, s7, 1
; GFX1250-SDAG-NEXT:    s_add_co_i32 s6, s6, s5
; GFX1250-SDAG-NEXT:    s_and_b32 s5, ttmp6, 15
; GFX1250-SDAG-NEXT:    s_mul_i32 s7, ttmp9, s7
; GFX1250-SDAG-NEXT:    s_getreg_b32 s8, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-SDAG-NEXT:    s_add_co_i32 s5, s5, s7
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s8, 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s5, ttmp9, s5
; GFX1250-SDAG-NEXT:    s_cselect_b32 s4, s4, s6
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5
; GFX1250-SDAG-NEXT:    v_mov_b32_e32 v2, s4
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_clause 0x1
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v2, s[2:3]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: workgroup_id_xy:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_bfe_u32 s6, ttmp6, 0x4000c
; GFX1250-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-GISEL-NEXT:    s_add_co_i32 s6, s6, 1
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    s_and_b32 s4, ttmp6, 15
; GFX1250-GISEL-NEXT:    s_mul_i32 s5, ttmp9, s6
; GFX1250-GISEL-NEXT:    s_getreg_b32 s6, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-GISEL-NEXT:    s_add_co_i32 s4, s4, s5
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s6, 0
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s4, ttmp9, s4
; GFX1250-GISEL-NEXT:    s_bfe_u32 s5, ttmp6, 0x40010
; GFX1250-GISEL-NEXT:    s_and_b32 s7, ttmp7, 0xffff
; GFX1250-GISEL-NEXT:    s_add_co_i32 s5, s5, 1
; GFX1250-GISEL-NEXT:    s_bfe_u32 s8, ttmp6, 0x40004
; GFX1250-GISEL-NEXT:    s_mul_i32 s5, s7, s5
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, s4
; GFX1250-GISEL-NEXT:    s_add_co_i32 s8, s8, s5
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s6, 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s4, s7, s8
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v2, s4
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_clause 0x1
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX1250-GISEL-NEXT:    s_endpgm
; GFX12-LABEL: workgroup_id_xy:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-NEXT:    s_and_b32 s4, ttmp7, 0xffff
; GFX12-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX12-NEXT:    v_mov_b32_e32 v2, s4
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX12-NEXT:    s_endpgm
  %idx = call i32 @llvm.amdgcn.workgroup.id.x()
  store i32 %idx, ptr addrspace(1) %ptrx
  %idy = call i32 @llvm.amdgcn.workgroup.id.y()
  store i32 %idy, ptr addrspace(1) %ptry

  ret void
}

define amdgpu_kernel void @workgroup_id_xyz(ptr addrspace(1) %ptrx, ptr addrspace(1) %ptry, ptr addrspace(1) %ptrz) {
; GFX9-LABEL: workgroup_id_xyz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0
; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x10
; GFX9-NEXT:    v_mov_b32_e32 v0, ttmp9
; GFX9-NEXT:    v_mov_b32_e32 v1, 0
; GFX9-NEXT:    s_and_b32 s6, ttmp7, 0xffff
; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-NEXT:    global_store_dword v1, v0, s[0:1]
; GFX9-NEXT:    v_mov_b32_e32 v0, s6
; GFX9-NEXT:    s_lshr_b32 s0, ttmp7, 16
; GFX9-NEXT:    global_store_dword v1, v0, s[2:3]
; GFX9-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-NEXT:    global_store_dword v1, v0, s[4:5]
; GFX9-NEXT:    s_endpgm
;
; GFX1200-LABEL: workgroup_id_xyz:
; GFX1200:       ; %bb.0:
; GFX1200-NEXT:    s_clause 0x1
; GFX1200-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1200-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
; GFX1200-NEXT:    s_and_b32 s6, ttmp7, 0xffff
; GFX1200-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX1200-NEXT:    s_lshr_b32 s7, ttmp7, 16
; GFX1200-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX1200-NEXT:    v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
; GFX1200-NEXT:    s_wait_kmcnt 0x0
; GFX1200-NEXT:    s_clause 0x2
; GFX1200-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1200-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX1200-NEXT:    global_store_b32 v1, v3, s[4:5]
; GFX1200-NEXT:    s_endpgm
;
; GFX1250-SDAG-LABEL: workgroup_id_xyz:
; GFX1250-SDAG:       ; %bb.0:
; GFX1250-SDAG-NEXT:    s_bfe_u32 s0, ttmp6, 0x40014
; GFX1250-SDAG-NEXT:    s_lshr_b32 s8, ttmp7, 16
; GFX1250-SDAG-NEXT:    s_add_co_i32 s9, s0, 1
; GFX1250-SDAG-NEXT:    s_clause 0x1
; GFX1250-SDAG-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-SDAG-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
; GFX1250-SDAG-NEXT:    s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT:    s_mul_i32 s4, s8, s9
; GFX1250-SDAG-NEXT:    s_bfe_u32 s9, ttmp6, 0x40010
; GFX1250-SDAG-NEXT:    s_bfe_u32 s5, ttmp6, 0x40008
; GFX1250-SDAG-NEXT:    s_and_b32 s10, ttmp7, 0xffff
; GFX1250-SDAG-NEXT:    s_add_co_i32 s9, s9, 1
; GFX1250-SDAG-NEXT:    s_bfe_u32 s11, ttmp6, 0x4000c
; GFX1250-SDAG-NEXT:    s_add_co_i32 s5, s5, s4
; GFX1250-SDAG-NEXT:    s_mul_i32 s4, s10, s9
; GFX1250-SDAG-NEXT:    s_bfe_u32 s9, ttmp6, 0x40004
; GFX1250-SDAG-NEXT:    s_add_co_i32 s11, s11, 1
; GFX1250-SDAG-NEXT:    s_add_co_i32 s9, s9, s4
; GFX1250-SDAG-NEXT:    s_and_b32 s4, ttmp6, 15
; GFX1250-SDAG-NEXT:    s_mul_i32 s11, ttmp9, s11
; GFX1250-SDAG-NEXT:    s_getreg_b32 s12, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-SDAG-NEXT:    s_add_co_i32 s4, s4, s11
; GFX1250-SDAG-NEXT:    s_cmp_eq_u32 s12, 0
; GFX1250-SDAG-NEXT:    s_cselect_b32 s4, ttmp9, s4
; GFX1250-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
; GFX1250-SDAG-NEXT:    s_cselect_b32 s4, s10, s9
; GFX1250-SDAG-NEXT:    s_cselect_b32 s5, s8, s5
; GFX1250-SDAG-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX1250-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX1250-SDAG-NEXT:    s_clause 0x2
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v2, s[2:3]
; GFX1250-SDAG-NEXT:    global_store_b32 v0, v3, s[6:7]
; GFX1250-SDAG-NEXT:    s_endpgm
;
; GFX1250-GISEL-LABEL: workgroup_id_xyz:
; GFX1250-GISEL:       ; %bb.0:
; GFX1250-GISEL-NEXT:    s_bfe_u32 s0, ttmp6, 0x4000c
; GFX1250-GISEL-NEXT:    s_and_b32 s1, ttmp6, 15
; GFX1250-GISEL-NEXT:    s_add_co_i32 s0, s0, 1
; GFX1250-GISEL-NEXT:    s_getreg_b32 s8, hwreg(HW_REG_IB_STS2, 6, 4)
; GFX1250-GISEL-NEXT:    s_mul_i32 s0, ttmp9, s0
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX1250-GISEL-NEXT:    s_add_co_i32 s1, s1, s0
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s8, 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s9, ttmp9, s1
; GFX1250-GISEL-NEXT:    s_bfe_u32 s0, ttmp6, 0x40010
; GFX1250-GISEL-NEXT:    s_and_b32 s10, ttmp7, 0xffff
; GFX1250-GISEL-NEXT:    s_add_co_i32 s0, s0, 1
; GFX1250-GISEL-NEXT:    s_bfe_u32 s11, ttmp6, 0x40004
; GFX1250-GISEL-NEXT:    s_mul_i32 s12, s10, s0
; GFX1250-GISEL-NEXT:    s_clause 0x1
; GFX1250-GISEL-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX1250-GISEL-NEXT:    s_load_b64 s[6:7], s[4:5], 0x10
; GFX1250-GISEL-NEXT:    s_add_co_i32 s11, s11, s12
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s8, 0
; GFX1250-GISEL-NEXT:    v_mov_b32_e32 v0, s9
; GFX1250-GISEL-NEXT:    s_wait_xcnt 0x0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s4, s10, s11
; GFX1250-GISEL-NEXT:    s_bfe_u32 s5, ttmp6, 0x40014
; GFX1250-GISEL-NEXT:    s_lshr_b32 s10, ttmp7, 16
; GFX1250-GISEL-NEXT:    s_add_co_i32 s5, s5, 1
; GFX1250-GISEL-NEXT:    s_bfe_u32 s11, ttmp6, 0x40008
; GFX1250-GISEL-NEXT:    s_mul_i32 s5, s10, s5
; GFX1250-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
; GFX1250-GISEL-NEXT:    s_add_co_i32 s11, s11, s5
; GFX1250-GISEL-NEXT:    s_cmp_eq_u32 s8, 0
; GFX1250-GISEL-NEXT:    s_cselect_b32 s5, s10, s11
; GFX1250-GISEL-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
; GFX1250-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT:    s_clause 0x2
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX1250-GISEL-NEXT:    global_store_b32 v1, v3, s[6:7]
; GFX1250-GISEL-NEXT:    s_endpgm
; GFX12-LABEL: workgroup_id_xyz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_clause 0x1
; GFX12-NEXT:    s_load_b128 s[0:3], s[4:5], 0x0
; GFX12-NEXT:    s_load_b64 s[4:5], s[4:5], 0x10
; GFX12-NEXT:    s_and_b32 s6, ttmp7, 0xffff
; GFX12-NEXT:    v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, 0
; GFX12-NEXT:    s_lshr_b32 s7, ttmp7, 16
; GFX12-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-NEXT:    v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_clause 0x2
; GFX12-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT:    global_store_b32 v1, v2, s[2:3]
; GFX12-NEXT:    global_store_b32 v1, v3, s[4:5]
; GFX12-NEXT:    s_endpgm
  %idx = call i32 @llvm.amdgcn.workgroup.id.x()
  store i32 %idx, ptr addrspace(1) %ptrx
  %idy = call i32 @llvm.amdgcn.workgroup.id.y()
  store i32 %idy, ptr addrspace(1) %ptry
  %idz = call i32 @llvm.amdgcn.workgroup.id.z()
  store i32 %idz, ptr addrspace(1) %ptrz

  ret void
}

declare i32 @llvm.amdgcn.workgroup.id.x()
declare i32 @llvm.amdgcn.workgroup.id.y()
declare i32 @llvm.amdgcn.workgroup.id.z()
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1250: {{.*}}
; GFX9-GISEL: {{.*}}
; GFX9-SDAG: {{.*}}