| //===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| |
| //===----------------------------------------------------------------------===// |
| // RISC-V processors supported. |
| //===----------------------------------------------------------------------===// |
| |
| class RISCVTuneInfo { |
| bits<8> PrefFunctionAlignment = 1; |
| bits<8> PrefLoopAlignment = 1; |
| |
| // Information needed by LoopDataPrefetch. |
| bits<16> CacheLineSize = 0; |
| bits<16> PrefetchDistance = 0; |
| bits<16> MinPrefetchStride = 1; |
| bits<32> MaxPrefetchIterationsAhead = -1; |
| |
| bits<32> MinimumJumpTableEntries = 5; |
| } |
| |
| def RISCVTuneInfoTable : GenericTable { |
| let FilterClass = "RISCVTuneInfo"; |
| let CppTypeName = "RISCVTuneInfo"; |
| let Fields = ["Name", "PrefFunctionAlignment", "PrefLoopAlignment", |
| "CacheLineSize", "PrefetchDistance", |
| "MinPrefetchStride", "MaxPrefetchIterationsAhead", |
| "MinimumJumpTableEntries"]; |
| } |
| |
| def getRISCVTuneInfo : SearchIndex { |
| let Table = RISCVTuneInfoTable; |
| let Key = ["Name"]; |
| } |
| |
| class GenericTuneInfo: RISCVTuneInfo; |
| |
| class RISCVProcessorModel<string n, |
| SchedMachineModel m, |
| list<SubtargetFeature> f, |
| list<SubtargetFeature> tunef = [], |
| string default_march = ""> |
| : ProcessorModel<n, m, f, tunef> { |
| string DefaultMarch = default_march; |
| } |
| |
| class RISCVTuneProcessorModel<string n, |
| SchedMachineModel m, |
| list<SubtargetFeature> tunef = [], |
| list<SubtargetFeature> f = []> |
| : ProcessorModel<n, m, f,tunef>; |
| |
| def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32", |
| NoSchedModel, |
| [Feature32Bit]>, |
| GenericTuneInfo; |
| def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64", |
| NoSchedModel, |
| [Feature64Bit]>, |
| GenericTuneInfo; |
| // Support generic for compatibility with other targets. The triple will be used |
| // to change to the appropriate rv32/rv64 version. |
| def : ProcessorModel<"generic", NoSchedModel, []>, GenericTuneInfo; |
| |
| def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtZicsr]>; |
| def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", |
| RocketModel, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtZicsr]>; |
| def ROCKET : RISCVTuneProcessorModel<"rocket", |
| RocketModel>; |
| |
| def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series", |
| SiFive7Model, |
| [TuneSiFive7]>; |
| |
| def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtZicsr, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34", |
| RocketModel, |
| [Feature32Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76", |
| SiFive7Model, |
| [Feature32Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtC], |
| [TuneSiFive7]>; |
| |
| def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21", |
| RocketModel, |
| [Feature64Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51", |
| RocketModel, |
| [Feature64Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54", |
| RocketModel, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76", |
| SiFive7Model, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC, |
| FeatureStdExtZihintpause], |
| [TuneSiFive7]>; |
| |
| def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54", |
| RocketModel, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC]>; |
| |
| def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74", |
| SiFive7Model, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC], |
| [TuneSiFive7]>; |
| |
| def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC, |
| FeatureStdExtV, |
| FeatureStdExtZvl512b, |
| FeatureStdExtZfh, |
| FeatureStdExtZvfh, |
| FeatureStdExtZba, |
| FeatureStdExtZbb], |
| [TuneSiFive7, |
| TuneDLenFactor2]>; |
| |
| def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC, |
| FeatureStdExtZicbop, |
| FeatureStdExtZicbom, |
| FeatureStdExtZicboz, |
| FeatureStdExtZihintntl, |
| FeatureStdExtZihintpause, |
| FeatureStdExtZihpm, |
| FeatureStdExtZba, |
| FeatureStdExtZbb, |
| FeatureStdExtZbs, |
| FeatureStdExtZfhmin], |
| [TuneConditionalCompressedMoveFusion]>; |
| |
| def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", |
| SyntacoreSCR1Model, |
| [Feature32Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtC], |
| [TuneNoDefaultUnroll]>; |
| |
| def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", |
| SyntacoreSCR1Model, |
| [Feature32Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtC], |
| [TuneNoDefaultUnroll]>; |
| |
| def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1", |
| NoSchedModel, |
| [Feature64Bit, |
| FeatureStdExtZifencei, |
| FeatureStdExtZicsr, |
| FeatureStdExtZicntr, |
| FeatureStdExtZihpm, |
| FeatureStdExtZihintpause, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC, |
| FeatureStdExtZba, |
| FeatureStdExtZbb, |
| FeatureStdExtZbc, |
| FeatureStdExtZbs, |
| FeatureStdExtZicbom, |
| FeatureStdExtZicbop, |
| FeatureStdExtZicboz, |
| FeatureVendorXVentanaCondOps], |
| [TuneVentanaVeyron, |
| TuneLUIADDIFusion, |
| TuneAUIPCADDIFusion, |
| TuneZExtHFusion, |
| TuneZExtWFusion, |
| TuneShiftedZExtWFusion, |
| TuneLDADDFusion]>; |
| |
| def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu", |
| NoSchedModel, |
| [Feature64Bit, |
| FeatureStdExtZicsr, |
| FeatureStdExtZifencei, |
| FeatureStdExtM, |
| FeatureStdExtA, |
| FeatureStdExtF, |
| FeatureStdExtD, |
| FeatureStdExtC, |
| FeatureStdExtZba, |
| FeatureStdExtZbb, |
| FeatureStdExtZbc, |
| FeatureStdExtZbs, |
| FeatureStdExtZkn, |
| FeatureStdExtZksed, |
| FeatureStdExtZksh, |
| FeatureStdExtSvinval, |
| FeatureStdExtZicbom, |
| FeatureStdExtZicboz]>; |
