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llvm/llvm-project/refs/heads/users/guochen2/amdgpu/true16-fix-isel-patterns/./llvm/test/CodeGen/AMDGPU/sad.ll
blob: c73e60022b62319af56f2f230a609cfb16b43256 [file] [edit]
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgpu7.00 < %s | FileCheck -check-prefix=GFX7-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu7.00 < %s | FileCheck -check-prefix=GFX7-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgpu12.5 < %s | FileCheck -check-prefix=GFX12-5-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.5 < %s | FileCheck -check-prefix=GFX12-5-GISEL %s
define amdgpu_kernel void @v_sad_u32_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: v_sad_u32 v0, s0, v0, v1
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s5, s2, s3
; GFX7-GISEL-NEXT: s_min_u32 s3, s2, s3
; GFX7-GISEL-NEXT: s_sub_i32 s3, s5, s3
; GFX7-GISEL-NEXT: s_add_i32 s3, s3, s4
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-GISEL-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s3, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_constant_pat1(ptr addrspace(1) %out, i32 %a) {
; GFX7-SDAG-LABEL: v_sad_u32_constant_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, 0x5a
; GFX7-SDAG-NEXT: s_mov_b32 s3, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s2, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_sad_u32 v0, s6, v0, 20
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_constant_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dword s3, s[4:5], 0xb
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s4, s3, 0x5a
; GFX7-GISEL-NEXT: s_min_u32 s3, s3, 0x5a
; GFX7-GISEL-NEXT: s_sub_i32 s3, s4, s3
; GFX7-GISEL-NEXT: s_add_i32 s3, s3, 20
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_constant_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s2, 0x5a
; GFX12-5-SDAG-NEXT: s_max_u32 s2, s2, 0x5a
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s2, s2, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s2, 20
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_constant_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s2, 0x5a
; GFX12-5-GISEL-NEXT: s_min_u32 s2, s2, 0x5a
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s2, s3, s2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, 20
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, 90
%t0 = select i1 %icmp0, i32 %a, i32 90
%icmp1 = icmp ule i32 %a, 90
%t1 = select i1 %icmp1, i32 %a, i32 90
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, 20
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: v_sad_u32 v0, s1, v0, v1
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_sub_u32 s5, s3, s2
; GFX7-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s3, s2, s3
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s3, s3, s5
; GFX7-GISEL-NEXT: s_add_i32 s3, s3, s4
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s1, s0
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b
%sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_sub_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX7-SDAG-NEXT: s_max_u32 s0, s0, s1
; GFX7-SDAG-NEXT: s_sub_i32 s0, s0, s3
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: s_add_i32 s0, s0, s2
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_sub_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s5, s2, s3
; GFX7-GISEL-NEXT: s_min_u32 s2, s2, s3
; GFX7-GISEL-NEXT: s_sub_i32 s2, s5, s2
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_sub_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s1, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_sub_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-GISEL-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s3, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s0, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1
store volatile i32 %ret0, ptr addrspace(5) poison
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_add_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: v_sad_u32 v0, s0, v0, v1
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_add_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s5, s2, s3
; GFX7-GISEL-NEXT: s_min_u32 s6, s2, s3
; GFX7-GISEL-NEXT: s_sub_i32 s5, s5, s6
; GFX7-GISEL-NEXT: s_add_i32 s4, s5, s4
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_add_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_add_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-GISEL-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s3, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c
store volatile i32 %ret, ptr addrspace(5) poison
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_max_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_max_u32 s3, s0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: buffer_store_dword v1, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: v_sad_u32 v0, s0, v0, v1
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_max_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s5, s2, s3
; GFX7-GISEL-NEXT: s_min_u32 s2, s2, s3
; GFX7-GISEL-NEXT: s_sub_i32 s2, s5, s2
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s5
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_max_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-SDAG-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s3, s0
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_max_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-GISEL-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s3, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
store volatile i32 %t0, ptr addrspace(5) poison
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_min_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: buffer_store_dword v1, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: v_sad_u32 v0, s0, v0, v1
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_min_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s5, s2, s3
; GFX7-GISEL-NEXT: s_min_u32 s2, s2, s3
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_sub_i32 s2, s5, s2
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_min_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s0, s1
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s0, s1
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s0
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_min_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s3, s0, s1
; GFX12-5-GISEL-NEXT: s_min_u32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s1, s3, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s1, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b
store volatile i32 %t1, ptr addrspace(5) poison
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_sub_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_sub_i32 s3, s0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: buffer_store_dword v1, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: v_sad_u32 v0, s1, v0, v1
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_sub_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_sub_u32 s5, s3, s2
; GFX7-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s2, s2, s3
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_cselect_b32 s2, s2, s5
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_sub_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0
; GFX12-5-SDAG-NEXT: s_max_u32 s4, s1, s0
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s1
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s4, s3
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s1, s3, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_sub_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s1, s0, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s1, s2
; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b
store volatile i32 %sub0, ptr addrspace(5) poison
%sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_multi_use_select_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-SDAG-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s14, -1
; GFX7-SDAG-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-SDAG-NEXT: s_add_u32 s12, s12, s11
; GFX7-SDAG-NEXT: s_addc_u32 s13, s13, 0
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_min_u32 s3, s1, s0
; GFX7-SDAG-NEXT: s_max_u32 s0, s1, s0
; GFX7-SDAG-NEXT: s_sub_i32 s0, s0, s3
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: s_add_i32 s0, s0, s2
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_multi_use_select_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_mov_b32 s12, SCRATCH_RSRC_DWORD0
; GFX7-GISEL-NEXT: s_mov_b32 s13, SCRATCH_RSRC_DWORD1
; GFX7-GISEL-NEXT: s_mov_b32 s14, -1
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dword s4, s[4:5], 0xd
; GFX7-GISEL-NEXT: s_mov_b32 s15, 0xe8f000
; GFX7-GISEL-NEXT: s_add_u32 s12, s12, s11
; GFX7-GISEL-NEXT: s_addc_u32 s13, s13, 0
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_sub_u32 s5, s3, s2
; GFX7-GISEL-NEXT: s_cselect_b32 s6, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s2, s2, s3
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s6, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s2, s2, s5
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: buffer_store_dword v0, v0, s[12:15], 0 offen
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_multi_use_select_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s3, s1, s0
; GFX12-5-SDAG-NEXT: s_max_u32 s0, s1, s0
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s1, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v2, s1
; GFX12-5-SDAG-NEXT: scratch_store_b32 off, v1, s0 scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_storecnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v2, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_multi_use_select_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_sub_co_u32 s3, s1, s0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s0, s2
; GFX12-5-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-5-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_storecnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b32 v2, v1, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b
%sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
store volatile i32 %ret0, ptr addrspace(5) poison
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_vector_pat1(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; GFX7-SDAG-LABEL: v_sad_u32_vector_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x15
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s15
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: v_sad_u32 v3, s11, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s14
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: v_sad_u32 v2, s10, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s13
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX7-SDAG-NEXT: v_sad_u32 v1, s9, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s12
; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, s0
; GFX7-SDAG-NEXT: v_sad_u32 v0, s8, v0, v4
; GFX7-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_vector_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x15
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s2, s8, s12
; GFX7-GISEL-NEXT: s_max_u32 s3, s9, s13
; GFX7-GISEL-NEXT: s_max_u32 s16, s10, s14
; GFX7-GISEL-NEXT: s_max_u32 s17, s11, s15
; GFX7-GISEL-NEXT: s_min_u32 s8, s8, s12
; GFX7-GISEL-NEXT: s_min_u32 s9, s9, s13
; GFX7-GISEL-NEXT: s_min_u32 s10, s10, s14
; GFX7-GISEL-NEXT: s_min_u32 s11, s11, s15
; GFX7-GISEL-NEXT: s_sub_i32 s2, s2, s8
; GFX7-GISEL-NEXT: s_sub_i32 s3, s3, s9
; GFX7-GISEL-NEXT: s_sub_i32 s8, s16, s10
; GFX7-GISEL-NEXT: s_sub_i32 s9, s17, s11
; GFX7-GISEL-NEXT: s_add_i32 s4, s2, s4
; GFX7-GISEL-NEXT: s_add_i32 s5, s3, s5
; GFX7-GISEL-NEXT: s_add_i32 s6, s8, s6
; GFX7-GISEL-NEXT: s_add_i32 s7, s9, s7
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_vector_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x2
; GFX12-5-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s4, s8, s12
; GFX12-5-SDAG-NEXT: s_max_u32 s5, s8, s12
; GFX12-5-SDAG-NEXT: s_min_u32 s8, s9, s13
; GFX12-5-SDAG-NEXT: s_max_u32 s9, s9, s13
; GFX12-5-SDAG-NEXT: s_min_u32 s12, s10, s14
; GFX12-5-SDAG-NEXT: s_max_u32 s10, s10, s14
; GFX12-5-SDAG-NEXT: s_min_u32 s13, s11, s15
; GFX12-5-SDAG-NEXT: s_max_u32 s11, s11, s15
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s4, s5, s4
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s5, s9, s8
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s8, s11, s13
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s9, s10, s12
; GFX12-5-SDAG-NEXT: s_add_co_i32 s8, s8, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s9, s9, s2
; GFX12-5-SDAG-NEXT: s_add_co_i32 s4, s4, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s5, s5, s1
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s4
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s9
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v3, s8
; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_vector_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x2
; GFX12-5-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s4, s8, s12
; GFX12-5-GISEL-NEXT: s_max_u32 s5, s9, s13
; GFX12-5-GISEL-NEXT: s_max_u32 s16, s10, s14
; GFX12-5-GISEL-NEXT: s_max_u32 s17, s11, s15
; GFX12-5-GISEL-NEXT: s_min_u32 s8, s8, s12
; GFX12-5-GISEL-NEXT: s_min_u32 s9, s9, s13
; GFX12-5-GISEL-NEXT: s_min_u32 s10, s10, s14
; GFX12-5-GISEL-NEXT: s_min_u32 s11, s11, s15
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s4, s4, s8
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s5, s5, s9
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s8, s16, s10
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s9, s17, s11
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s4, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s5, s1
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s8, s2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s3, s9, s3
; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX12-5-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt <4 x i32> %a, %b
%t0 = select <4 x i1> %icmp0, <4 x i32> %a, <4 x i32> %b
%icmp1 = icmp ule <4 x i32> %a, %b
%t1 = select <4 x i1> %icmp1, <4 x i32> %a, <4 x i32> %b
%ret0 = sub <4 x i32> %t0, %t1
%ret = add <4 x i32> %ret0, %c
store <4 x i32> %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_vector_pat2(ptr addrspace(1) %out, <4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
; GFX7-SDAG-LABEL: v_sad_u32_vector_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x15
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s15
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: v_sad_u32 v3, s11, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s14
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s2
; GFX7-SDAG-NEXT: v_sad_u32 v2, s10, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s13
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s1
; GFX7-SDAG-NEXT: v_sad_u32 v1, s9, v0, v1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s12
; GFX7-SDAG-NEXT: v_mov_b32_e32 v4, s0
; GFX7-SDAG-NEXT: v_sad_u32 v0, s8, v0, v4
; GFX7-SDAG-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_vector_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x15
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s8, s12
; GFX7-GISEL-NEXT: s_cselect_b32 s2, 1, 0
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s9, s13
; GFX7-GISEL-NEXT: s_cselect_b32 s3, 1, 0
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s10, s14
; GFX7-GISEL-NEXT: s_cselect_b32 s16, 1, 0
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s11, s15
; GFX7-GISEL-NEXT: s_cselect_b32 s17, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s18, s8, s12
; GFX7-GISEL-NEXT: s_sub_i32 s19, s9, s13
; GFX7-GISEL-NEXT: s_sub_i32 s20, s10, s14
; GFX7-GISEL-NEXT: s_sub_i32 s21, s11, s15
; GFX7-GISEL-NEXT: s_sub_i32 s8, s12, s8
; GFX7-GISEL-NEXT: s_sub_i32 s9, s13, s9
; GFX7-GISEL-NEXT: s_sub_i32 s10, s14, s10
; GFX7-GISEL-NEXT: s_sub_i32 s11, s15, s11
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s2, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s2, s18, s8
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s3, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s3, s19, s9
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s16, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s8, s20, s10
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s17, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s9, s21, s11
; GFX7-GISEL-NEXT: s_add_i32 s4, s2, s4
; GFX7-GISEL-NEXT: s_add_i32 s5, s3, s5
; GFX7-GISEL-NEXT: s_add_i32 s6, s8, s6
; GFX7-GISEL-NEXT: s_add_i32 s7, s9, s7
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT: v_mov_b32_e32 v1, s5
; GFX7-GISEL-NEXT: v_mov_b32_e32 v2, s6
; GFX7-GISEL-NEXT: v_mov_b32_e32 v3, s7
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_vector_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x2
; GFX12-5-SDAG-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_min_u32 s4, s8, s12
; GFX12-5-SDAG-NEXT: s_max_u32 s5, s8, s12
; GFX12-5-SDAG-NEXT: s_min_u32 s8, s9, s13
; GFX12-5-SDAG-NEXT: s_max_u32 s9, s9, s13
; GFX12-5-SDAG-NEXT: s_min_u32 s12, s10, s14
; GFX12-5-SDAG-NEXT: s_max_u32 s10, s10, s14
; GFX12-5-SDAG-NEXT: s_min_u32 s13, s11, s15
; GFX12-5-SDAG-NEXT: s_max_u32 s11, s11, s15
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s4, s5, s4
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s5, s9, s8
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s8, s11, s13
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s9, s10, s12
; GFX12-5-SDAG-NEXT: s_add_co_i32 s8, s8, s3
; GFX12-5-SDAG-NEXT: s_add_co_i32 s9, s9, s2
; GFX12-5-SDAG-NEXT: s_add_co_i32 s4, s4, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s5, s5, s1
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s4
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s9
; GFX12-5-SDAG-NEXT: v_mov_b32_e32 v3, s8
; GFX12-5-SDAG-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_vector_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x2
; GFX12-5-GISEL-NEXT: s_load_b256 s[8:15], s[4:5], 0x34 nv
; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x54 nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v4, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s8, s12
; GFX12-5-GISEL-NEXT: s_cselect_b32 s16, 1, 0
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s9, s13
; GFX12-5-GISEL-NEXT: s_cselect_b32 s17, 1, 0
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s10, s14
; GFX12-5-GISEL-NEXT: s_cselect_b32 s18, 1, 0
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s11, s15
; GFX12-5-GISEL-NEXT: s_cselect_b32 s19, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s4, s8, s12
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s5, s9, s13
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s20, s10, s14
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s21, s11, s15
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s8, s12, s8
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s9, s13, s9
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s10, s14, s10
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s11, s15, s11
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s16, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, s4, s8
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s17, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s5, s5, s9
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s18, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s8, s20, s10
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s19, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s9, s21, s11
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s4, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s1, s5, s1
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s8, s2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s3, s9, s3
; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX12-5-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX12-5-GISEL-NEXT: global_store_b128 v4, v[0:3], s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt <4 x i32> %a, %b
%sub0 = sub <4 x i32> %a, %b
%sub1 = sub <4 x i32> %b, %a
%ret0 = select <4 x i1> %icmp0, <4 x i32> %sub0, <4 x i32> %sub1
%ret = add <4 x i32> %ret0, %c
store <4 x i32> %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16 %b, i16 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_i16_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_mov_b32 s5, s1
; GFX7-SDAG-NEXT: s_lshr_b32 s1, s2, 16
; GFX7-SDAG-NEXT: s_mov_b32 s4, s0
; GFX7-SDAG-NEXT: s_and_b32 s0, s2, 0xffff
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s1
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s3
; GFX7-SDAG-NEXT: v_sad_u32 v0, s0, v0, v1
; GFX7-SDAG-NEXT: buffer_store_short v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_i16_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_lshr_b32 s4, s2, 16
; GFX7-GISEL-NEXT: s_and_b32 s5, s2, 0xffff
; GFX7-GISEL-NEXT: s_max_u32 s6, s5, s4
; GFX7-GISEL-NEXT: s_min_u32 s4, s5, s4
; GFX7-GISEL-NEXT: s_sub_i32 s4, s6, s4
; GFX7-GISEL-NEXT: s_add_i32 s3, s4, s3
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s3
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_i16_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-5-SDAG-NEXT: s_and_b32 s2, s2, 0xffff
; GFX12-5-SDAG-NEXT: s_and_b32 s4, s4, 0xffff
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_min_u32 s5, s2, s4
; GFX12-5-SDAG-NEXT: s_max_u32 s2, s2, s4
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s2, s2, s5
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s2, s3
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-5-SDAG-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_i16_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_lshr_b32 s4, s2, 16
; GFX12-5-GISEL-NEXT: s_and_b32 s2, 0xffff, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_max_u32 s5, s2, s4
; GFX12-5-GISEL-NEXT: s_min_u32 s2, s2, s4
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s2, s5, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, s3
; GFX12-5-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-5-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i16 %a, %b
%t0 = select i1 %icmp0, i16 %a, i16 %b
%icmp1 = icmp ule i16 %a, %b
%t1 = select i1 %icmp1, i16 %a, i16 %b
%ret0 = sub i16 %t0, %t1
%ret = add i16 %ret0, %c
store i16 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_i16_pat2(ptr addrspace(1) %out) {
; GFX7-SDAG-LABEL: v_sad_u32_i16_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s3, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s2, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ushort v0, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ushort v1, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ushort v2, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_sad_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_i16_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ushort v0, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ushort v1, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ushort v2, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s4, s5
; GFX7-GISEL-NEXT: s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s8, s4, s5
; GFX7-GISEL-NEXT: s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s7, 0
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s6, v2
; GFX7-GISEL-NEXT: s_cselect_b32 s4, s8, s4
; GFX7-GISEL-NEXT: s_add_i32 s4, s4, s6
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_i16_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: global_load_u16 v0, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_xcnt 0x0
; GFX12-5-SDAG-NEXT: global_load_u16 v1, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: global_load_u16 v2, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX12-5-SDAG-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX12-5-SDAG-NEXT: v_min_u32_e32 v3, v0, v1
; GFX12-5-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, v0, v3
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-5-SDAG-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_i16_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: global_load_u16 v0, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: s_wait_xcnt 0x0
; GFX12-5-GISEL-NEXT: global_load_u16 v1, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-5-GISEL-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-GISEL-NEXT: s_and_b32 s4, 0xffff, s2
; GFX12-5-GISEL-NEXT: global_load_u16 v2, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_and_b32 s5, 0xffff, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s4, s5
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s6, s2, s3
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s2, s3, s2
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s2, s6, s2
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s5, v2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, s5
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%a = load volatile i16, ptr addrspace(1) poison
%b = load volatile i16, ptr addrspace(1) poison
%c = load volatile i16, ptr addrspace(1) poison
%icmp0 = icmp ugt i16 %a, %b
%sub0 = sub i16 %a, %b
%sub1 = sub i16 %b, %a
%ret0 = select i1 %icmp0, i16 %sub0, i16 %sub1
%ret = add i16 %ret0, %c
store i16 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_i8_pat1(ptr addrspace(1) %out, i8 %a, i8 %b, i8 %c) {
; GFX7-SDAG-LABEL: v_sad_u32_i8_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s3, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s2, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_and_b32 s4, s6, 0xff
; GFX7-SDAG-NEXT: s_bfe_u32 s5, s6, 0x80008
; GFX7-SDAG-NEXT: s_lshr_b32 s6, s6, 16
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s5
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s6
; GFX7-SDAG-NEXT: v_sad_u32 v0, s4, v0, v1
; GFX7-SDAG-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_i8_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_lshr_b32 s3, s2, 16
; GFX7-GISEL-NEXT: s_and_b32 s4, s2, 0xff
; GFX7-GISEL-NEXT: s_bfe_u32 s2, s2, 0x80008
; GFX7-GISEL-NEXT: s_max_u32 s5, s4, s2
; GFX7-GISEL-NEXT: s_min_u32 s2, s4, s2
; GFX7-GISEL-NEXT: s_sub_i32 s2, s5, s2
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s3
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_i8_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_lshr_b32 s3, s2, 8
; GFX12-5-SDAG-NEXT: s_and_b32 s4, s2, 0xff
; GFX12-5-SDAG-NEXT: s_and_b32 s3, s3, 0xff
; GFX12-5-SDAG-NEXT: s_lshr_b32 s2, s2, 16
; GFX12-5-SDAG-NEXT: s_min_u32 s5, s4, s3
; GFX12-5-SDAG-NEXT: s_max_u32 s3, s4, s3
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s3, s5
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s3, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-5-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_i8_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_lshr_b32 s3, s2, 8
; GFX12-5-GISEL-NEXT: s_and_b32 s4, s2, 0xff
; GFX12-5-GISEL-NEXT: s_and_b32 s3, s3, 0xff
; GFX12-5-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX12-5-GISEL-NEXT: s_max_u32 s5, s4, s3
; GFX12-5-GISEL-NEXT: s_min_u32 s3, s4, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s3, s5, s3
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s3, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i8 %a, %b
%t0 = select i1 %icmp0, i8 %a, i8 %b
%icmp1 = icmp ule i8 %a, %b
%t1 = select i1 %icmp1, i8 %a, i8 %b
%ret0 = sub i8 %t0, %t1
%ret = add i8 %ret0, %c
store i8 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_i8_pat2(ptr addrspace(1) %out) {
; GFX7-SDAG-LABEL: v_sad_u32_i8_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s3, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s2, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: buffer_load_ubyte v2, off, s[0:3], 0 glc
; GFX7-SDAG-NEXT: s_waitcnt vmcnt(0)
; GFX7-SDAG-NEXT: v_sad_u32 v0, v0, v1, v2
; GFX7-SDAG-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_i8_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: buffer_load_ubyte v2, off, s[0:3], 0 glc
; GFX7-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s4, v0
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s5, v1
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s4, s5
; GFX7-GISEL-NEXT: s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s8, s4, s5
; GFX7-GISEL-NEXT: s_sub_i32 s4, s5, s4
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s7, 0
; GFX7-GISEL-NEXT: v_readfirstlane_b32 s6, v2
; GFX7-GISEL-NEXT: s_cselect_b32 s4, s8, s4
; GFX7-GISEL-NEXT: s_add_i32 s4, s4, s6
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s4
; GFX7-GISEL-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_i8_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: global_load_u8 v0, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_xcnt 0x0
; GFX12-5-SDAG-NEXT: global_load_u8 v1, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-SDAG-NEXT: global_load_u8 v2, v[0:1], off scope:SCOPE_SYS
; GFX12-5-SDAG-NEXT: s_wait_loadcnt 0x0
; GFX12-5-SDAG-NEXT: v_min_u32_e32 v3, v0, v1
; GFX12-5-SDAG-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, v0, v3
; GFX12-5-SDAG-NEXT: v_add_nc_u32_e32 v0, v0, v2
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_i8_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: global_load_u8 v0, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: s_wait_xcnt 0x0
; GFX12-5-GISEL-NEXT: global_load_u8 v1, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-5-GISEL-NEXT: ; kill: killed $vgpr0_vgpr1
; GFX12-5-GISEL-NEXT: global_load_u8 v2, v[0:1], off scope:SCOPE_SYS
; GFX12-5-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s2, s3
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s6, s2, s3
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s2, s3, s2
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s2, s6, s2
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s5, v2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, s5
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%a = load volatile i8, ptr addrspace(1) poison
%b = load volatile i8, ptr addrspace(1) poison
%c = load volatile i8, ptr addrspace(1) poison
%icmp0 = icmp ugt i8 %a, %b
%sub0 = sub i8 %a, %b
%sub1 = sub i8 %b, %a
%ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1
%ret = add i8 %ret0, %c
store i8 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @s_sad_u32_i8_pat2(ptr addrspace(1) %out, i8 zeroext %a, i8 zeroext %b, i8 zeroext %c) {
; GFX7-SDAG-LABEL: s_sad_u32_i8_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dword s6, s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s3, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s2, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_and_b32 s4, s6, 0xff
; GFX7-SDAG-NEXT: s_bfe_u32 s5, s6, 0x80008
; GFX7-SDAG-NEXT: s_lshr_b32 s6, s6, 16
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s5
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s6
; GFX7-SDAG-NEXT: v_sad_u32 v0, s4, v0, v1
; GFX7-SDAG-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: s_sad_u32_i8_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dword s2, s[4:5], 0xb
; GFX7-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_lshr_b32 s3, s2, 8
; GFX7-GISEL-NEXT: s_lshr_b32 s4, s2, 16
; GFX7-GISEL-NEXT: s_and_b32 s5, s2, 0xff
; GFX7-GISEL-NEXT: s_and_b32 s6, s3, 0xff
; GFX7-GISEL-NEXT: s_cmp_gt_u32 s5, s6
; GFX7-GISEL-NEXT: s_cselect_b32 s5, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s6, s2, s3
; GFX7-GISEL-NEXT: s_sub_i32 s2, s3, s2
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s5, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s2, s6, s2
; GFX7-GISEL-NEXT: s_add_i32 s2, s2, s4
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX7-GISEL-NEXT: s_mov_b32 s2, -1
; GFX7-GISEL-NEXT: s_mov_b32 s3, 0xf000
; GFX7-GISEL-NEXT: buffer_store_byte v0, off, s[0:3], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: s_sad_u32_i8_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_lshr_b32 s3, s2, 8
; GFX12-5-SDAG-NEXT: s_and_b32 s4, s2, 0xff
; GFX12-5-SDAG-NEXT: s_and_b32 s3, s3, 0xff
; GFX12-5-SDAG-NEXT: s_lshr_b32 s2, s2, 16
; GFX12-5-SDAG-NEXT: s_min_u32 s5, s4, s3
; GFX12-5-SDAG-NEXT: s_max_u32 s3, s4, s3
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s3, s5
; GFX12-5-SDAG-NEXT: s_add_co_i32 s2, s3, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-5-SDAG-NEXT: global_store_b8 v0, v1, s[0:1]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: s_sad_u32_i8_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_lshr_b32 s3, s2, 8
; GFX12-5-GISEL-NEXT: s_and_b32 s4, s2, 0xff
; GFX12-5-GISEL-NEXT: s_and_b32 s5, s3, 0xff
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_cmp_gt_u32 s4, s5
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s5, s2, s3
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s3, s3, s2
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s3, s5, s3
; GFX12-5-GISEL-NEXT: s_lshr_b32 s2, s2, 16
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s3, s2
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i8 %a, %b
%sub0 = sub i8 %a, %b
%sub1 = sub i8 %b, %a
%ret0 = select i1 %icmp0, i8 %sub0, i8 %sub1
%ret = add i8 %ret0, %c
store i8 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {
; GFX7-SDAG-LABEL: v_sad_u32_mismatched_operands_pat1:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: s_max_u32 s8, s0, s1
; GFX7-SDAG-NEXT: s_cmp_le_u32 s0, s1
; GFX7-SDAG-NEXT: s_cselect_b32 s0, s0, s3
; GFX7-SDAG-NEXT: s_sub_i32 s0, s8, s0
; GFX7-SDAG-NEXT: s_add_i32 s0, s0, s2
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_mismatched_operands_pat1:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_mov_b32 s6, -1
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_max_u32 s7, s0, s1
; GFX7-GISEL-NEXT: s_cmp_le_u32 s0, s1
; GFX7-GISEL-NEXT: s_cselect_b32 s0, s0, s3
; GFX7-GISEL-NEXT: s_sub_i32 s0, s7, s0
; GFX7-GISEL-NEXT: s_add_i32 s0, s0, s2
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX7-GISEL-NEXT: s_mov_b32 s7, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_mismatched_operands_pat1:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_max_u32 s4, s0, s1
; GFX12-5-SDAG-NEXT: s_cmp_le_u32 s0, s1
; GFX12-5-SDAG-NEXT: s_cselect_b32 s0, s0, s3
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s0, s4, s0
; GFX12-5-SDAG-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX12-5-SDAG-NEXT: global_store_b32 v0, v1, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_mismatched_operands_pat1:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_max_u32 s4, s0, s1
; GFX12-5-GISEL-NEXT: s_cmp_le_u32 s0, s1
; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s3
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s4, s0
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %d
%ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @v_sad_u32_mismatched_operands_pat2(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {
; GFX7-SDAG-LABEL: v_sad_u32_mismatched_operands_pat2:
; GFX7-SDAG: ; %bb.0:
; GFX7-SDAG-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-SDAG-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-SDAG-NEXT: s_mov_b32 s7, 0xf000
; GFX7-SDAG-NEXT: s_mov_b32 s6, -1
; GFX7-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-SDAG-NEXT: v_mov_b32_e32 v0, s0
; GFX7-SDAG-NEXT: s_sub_i32 s0, s0, s3
; GFX7-SDAG-NEXT: v_mov_b32_e32 v1, s0
; GFX7-SDAG-NEXT: v_sub_i32_e32 v0, vcc, s1, v0
; GFX7-SDAG-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX7-SDAG-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-SDAG-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-SDAG-NEXT: s_endpgm
;
; GFX7-GISEL-LABEL: v_sad_u32_mismatched_operands_pat2:
; GFX7-GISEL: ; %bb.0:
; GFX7-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; GFX7-GISEL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GFX7-GISEL-NEXT: s_mov_b32 s6, -1
; GFX7-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-GISEL-NEXT: s_sub_u32 s1, s1, s0
; GFX7-GISEL-NEXT: s_cselect_b32 s7, 1, 0
; GFX7-GISEL-NEXT: s_sub_i32 s0, s0, s3
; GFX7-GISEL-NEXT: s_cmp_lg_u32 s7, 0
; GFX7-GISEL-NEXT: s_cselect_b32 s0, s0, s1
; GFX7-GISEL-NEXT: s_add_i32 s0, s0, s2
; GFX7-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX7-GISEL-NEXT: s_mov_b32 s7, 0xf000
; GFX7-GISEL-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX7-GISEL-NEXT: s_endpgm
;
; GFX12-5-SDAG-LABEL: v_sad_u32_mismatched_operands_pat2:
; GFX12-5-SDAG: ; %bb.0:
; GFX12-5-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-SDAG-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-SDAG-NEXT: v_nop
; GFX12-5-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-SDAG-NEXT: s_clause 0x1
; GFX12-5-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv
; GFX12-5-SDAG-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-5-SDAG-NEXT: s_sub_co_i32 s3, s0, s3
; GFX12-5-SDAG-NEXT: v_sub_co_u32 v0, s0, s1, s0
; GFX12-5-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-5-SDAG-NEXT: v_cndmask_b32_e64 v0, v0, s3, s0
; GFX12-5-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
; GFX12-5-SDAG-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-SDAG-NEXT: s_endpgm
;
; GFX12-5-GISEL-LABEL: v_sad_u32_mismatched_operands_pat2:
; GFX12-5-GISEL: ; %bb.0:
; GFX12-5-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX12-5-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX12-5-GISEL-NEXT: v_nop
; GFX12-5-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX12-5-GISEL-NEXT: s_clause 0x1
; GFX12-5-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c nv
; GFX12-5-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x24 nv
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: s_sub_co_u32 s1, s1, s0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s4, 1, 0
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s0, s0, s3
; GFX12-5-GISEL-NEXT: s_cmp_lg_u32 s4, 0
; GFX12-5-GISEL-NEXT: s_cselect_b32 s0, s0, s1
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s0, s0, s2
; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX12-5-GISEL-NEXT: global_store_b32 v1, v0, s[6:7]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %d
%sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
%ret = add i32 %ret0, %c
store i32 %ret, ptr addrspace(1) %out
ret void
}